|The circuit shown here is from the long board schematic 1540008. This logic was integrated in the PLA (Programmable Logic Array) on the short boards.|
During a read operation, data from the read amplifiers is applied to the CLR input of counter UF4. The outputs, C and D, are shaped by the 'NOR' gate UE5. UE5 outputs the serial data on pin 1, then it is converted to parallel data by UD2. The output of UD2 is latched by UC3. The serial bits are counted by UE4, when 8 bits have been counted, UF3 pin 12 goes "low", UC1 pin 10 goes "high", and UF3 pin 8 goes "low" indicating a byte is ready to be read by the processor. UC2 monitors the parallel output of UD2, when all 8 bits are "1", the output pin 9 goes "low" indicating a sync bit has been read.
|This page has been created by Sami Rautiainen.|
|Read the small print.||Last updated April 18, 1998.|