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11TESTInput used in design verification.
2-92-9YB0-YB7Data input/output lines for read/write operation.
11,1211,12STP0,STP1Input to stepper driver.
1313MTRControl line used to activate the stepper motor.
1414AWrite protect input. Indicates disk is write protected.
15,1615,16DS0,DS1Inputs used to produce the binary count for the frequency divide ratio.
1717SYNCSync output.
1818TEDA low input clears the BYTE line in 2 MHz mode. A high sets 1541 mode.
1919OEInput to read/write block to set mode. 0 for Write, 1 for Read.
2020ACCLInput select line for the CPU clock. 0 for 1541 - 1 MHz, 1 for 1571 - 2 MHz.
2123OSC16 MHz clock input.
2224ATNAAttention acknowledge input.
2325ATNIAttention line input from serial bus.
2426ATNAttention data input from serial bus.
25-2827-30Y0-Y3Control output lines for the 4 phases of the stepper motor.
2931XRWRAM write enable output.
3133CLRHigh input when the read data is logical 1.
3234PLLInput from the 20 pin gate array. Clock compensation.
3335LOCKIndicates the PLL LOCK status. When logical 1, PLL is locked. When 0, the internal clock is used for sampling data.
3436R/WR/W select input.
35,3637,38Q,QxWrite pulse outputs.
3739CKClock select output - 1 or 2 MHz.
3840BWrite enable output.
3941SOEEnable byte input.
4042BYTEData latched output.

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This page has been created by Frank Kontros.
Last updated May 21th, 1998.