PIN ASSIGNMENT
LOGIC DIAGRAM
|
TRUTH TABLE
OPERATING MODE |
INPUTS |
OUTPUTS |
|
|
CP |
D |
|
|
Asyn. Set
Asyn. Reset (Clear)
Undetermined
Load "1" (Set)
Load "0" (Reset)
|
L H L H H
|
H L L H H
|
X X X
|
X X X h l
|
H L H H L
|
L H L L H
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H = HIGH voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
L = LOW voltage level steady state.
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = don't care.
= LOW-to-HIGH clock transition.
NOTE
Both outputs will be HIGH while both and are LOW.
But the output states are unpredictable if and go HIGH simultaneously.
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