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System Specification for C65Fred BowenMarch 1, 1991

2.3.3 Functional Description

2.3.3.1 Pin Description

PIN
NAME
PIN
NUMBER
SIGNAL
DIRECTION
DESCRIPTION
VSS 1 IN This is the power ground signal (0 volts).
VCC 2,42 IN This is the power supply signal (+5 volts).
SPB,
SPA
3
5
I/O
I/O
The SPA and SPB signals are open-drain and bi-directional, each with a 3K ohm (min.) passive pull-up. The SPA and SPB signals are the data lines used by the two 8-bit synchronous serial port registers. In input mode, SPA and SPB are clocked into the device on the rising edge of the CNTA and CNTB clocks, respectively. In the output mode, SPA and SPB change on the falling edge of the CNTA and CNTB clocks, respectively.
CNTB,
CNTA,
4
6
I/O
I/O
The CNTA and CNTB signals are open-drain and bi-directional, each with a 3K ohm (min.) passive pull-up. These pins are internally synchronized to the RH0 clock and then used to clock the synchronous serial registers, in input mode. In output mode, each pin will reflect the clock signal derived from the corresponding timer.
FLAGA/
FLAGB/
7
8
I/O
IN
The FLAGA/ and FLAGB/ inputs are negative edge sensitive input signals. A passive pull-up (3K ohm min) is tied on each of these pins. They are internally synchronized to the RH0 clock and are used as general purpose interrupt inputs; Any negative transition on either of these signals will cause the device to start an interrupt sequence, provided that the proper bit is set in each of the interrupt mask registers. The device will drop the IRQ/ line to indicate that an interrupt sequence is underway.
  *** When the FAST SERIAL MODE is enabled the CNTA, SPA and FLAGA/ lines will not function as described above. See section 2.5.6 for FAST SERIAL MODE description. ***
A0-A19 9 thru 28 I/O Address Bus - This is a 20 bit bi-directional bus with tri-state outputs. The output of each address line is TTL compatible, capable of driving two standard TTL loads and 55 pf. When the AEC or DMA/ line goes low, the bus goes tri-state. If AEC only is low, A17, A18 and A19 will each reflect the state of the A16 line. During an 1/0 access (10/ is low), A0-A3, AS and A9 are used to select an internal 1/0 register. If AEC is high, the bus will be driven by the CPU and A16-A19 will point to a mapped memory location (if MAP/ is low). If memory is not mapped (MAP/ is high), A16-A19 will be low.



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