PRC57	73	I/O	This is an open drain bi-directional signal with a passive pull-up 1K ohm min). Bit 7 of PORT C is always configured as an input; the bit will give the status of the PRC57 line anytime the the port is read, regardless of what is written' in the data direction register If bit 5 of PORT C is set as an input, the PRC57 line will be pulled low; reading the port bit will give a high. If bit 5 is configured as an output, PRC57 will be pulled low if bit 5 in the port data register is high, otherwise the PRC57 line will float to a high.
PRE0,PRE1	83, 84	I/O	This a 2-bit port with each line having a passive pull-up (min. 3K ohm) as well as active pull-up and pull-down transistors. Each individual port line may be programmed to be eith input or output.
BAUDCLK	74	IN	This input is a 7MHz clock used to drive the UART Baud Rate Generator, and is assumed to be synchronous with the RH0 clock. This clock is also divided down to 1MHz to drive the interval timers, and down to 10Hz to drive the TOD timers. This clock is also used to time out the POR and RESTORE (RSTR*) circuits.
TEST	75	IN	When this input goes to a high state, the device will operate in a test mode. The test mode will allow the BAUDCLK dividers to be initialized and the TOD and interval timers to be driven directly by the BAUDCLK clock, bypassing all the dividers.
TXD	76	OUT	This is the UART transmit data output line. The LSB of the Transmit Data Register is the first data bit transmitted. The data transmission rate (baud rate) is determined by the value written to the Baud Rate Timer latches.
RXD	77	IN	This is the UART receive data input line and is connected to a passive pull-up (1K ohm min) The first data bit received is loaded into the LSB of the Receive Data Register. The receive data rate must be the same a$ that determined by the value written to the Baud Rate Timer latches.