NMI/	78	I/O	The NMI/ pin is an open drain bi-directional signal. A passive pull-up (3K ohms minimum) is tied on this pin, allowing multiple NMI/ sources to be tied together. A negative transition on this pin requests a non-maskable interrupt sequence to be generated by the microprocessor. The interrupt sequence will begin with the first PSYNC: after a multiple-cycle opcode. NMI/ inputs cannot be masked by the processor status register I flag. The two program counter bytes PCH and PCL, and the processor status register P, are pushed onto the stack. Then the program counter bytes PCL and PCH are loaded from memory addresses FFFA and FFFB, respectively. NOTE: Since this interrupt is non-maskable, another NMI/ can occur before the first is finished. Care should be taken to avoid this. The NMI/ line is normally off (high impedance) and the device will activate it low as described in the functional description. AEC and DMA/ must be high for any interrupt to be recognized.
IRQ/	79	I/O	The Interrupt Request line (IRQ/) is an open drain bi-directional signal. A passive pull up (3K ohms minimum) is tied on this pin, allowing multiple IRQ/ sources to be connected together. This pin is sampled during PH2 and when a negative transition is detected an interrupt will be activated, only if the mask flag (I) in the status register is low. The interrupt sequence will begin with the first PSYNC after a multiple-cycle opcode. The two program counter bytes PCH and PCL, and the processor status register P, are stored onto the stack; the interrupt mask flag is set high so that no further IRQ/'s may occur. At the end of this cycle, the program counter low byte (PCL) will be loaded from address FFFE and the high byte (PCH) from FFFF, thus transferring program control to the vector located at this addresses. The IRQ/ line is normally off (high impedance) and the device will activate it low as described in the functional description AEC and DMA/ must be high for any interrupt to be recognized.