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System Specification for C65Fred BowenMarch 1, 1991

2.3.5.7 Interrupt Control Registers (ICRA, ICRB)

These registers control the following Sources of interrupts:

i. Underflows from TIMER A, TIMER B, TIMER C and TIMER D
ii. TODA ALARM and TODB ALARM.
iii. SERIALA and SERIALB Port full/empty conditions.
iv. FLAGA/ and FLAGB/ low transitions.

The ICRA and ICRB registers each provides masking and interrupt information. ICRA and ICRB each consists of a write-only MASK register and a read-only-DATA register. Any interrupt will set the corresponding bit in the DATA register. Any interrupt which is enabled by the MASK register will s?t the IR bit (MSB) of its corresponding DATA register and bring the IRQ/ pin low. In a multi-chip system, the IR bit (IRA of ICRA or IRB of ICRB) can be polled to detect which chip has generated an interrupt request. The interrupt DATA register is cleared and the IRQ/ lint returns high following a read of the DATA register. Since each interrupt sets and interrupt bit regardless of the MASK, and each interrupt bit can be selectively masked to prevent the generation of a processor interrupt, it is possible to intermix polled interrupts with true interrupts. However, polling either of the IR bits will cause its corresponding DATA register to clear, therefore, it is up to the user to preserve the information contained in the DATA registers if any polled interrupts were present.

Both MASK (ICRA, ICRB) registers provide convenient control of individual mask bits. When writing to a MASK register, if bit 7 of the data written (corresponding to AS/C in ICRA, or BS/C in ICRB) is a ZERO, any mask bit written with a one will be cleared, while those bits written with a zero will be unaffected. In order for an interrupt flag to set the IR bit and generate an Interrupt Request, the corresponding MASK bit must be set in the corresponding MASK Register.



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