|System Specification for C65||Fred Bowen||March 1, 1991|
The device contains seven registers to control the different UART modes of operation. Section 2.2 describes how to access these registers.
The UART modes can be programmed by accessing the UART control register, URCR, whose bits function as described below.
1=Even Parity. If parity is enabled, the transmitter will
assert the parity bit (P) to a low when "even" parity data is
transmitted, otherwise it will pull it high. The receiver
checks that the parity bit is asserted, or low, if the data
received has even parity; if the bit is not asserted, the
device will indicate a parity error,
0=Odd Parity. - If parity is enabled, the transmitter will pull the parity bit (P) low, when "odd" parity data is transmitted, otherwise it will pull it high. The receiver checks that the parity bit is asserted if the data received has odd parity; if the bit is not asserted when data had odd parity, the device will indicate a parity error.
1= Parity Enabled.
0= Parity Disabled. The transmitter and receiver will not allocate a parity bit in the data, instead a stop bit will be used in its place. See the Data Configuration chart below
These two bits are used to select the number of bits per
character to be transmitted or received. 5,6,7 or 8 bits
per character may be selected as follows:
These two bits select whether operations will be
asynchronous or synchronous for the transmitter and/or
receiver. The actual selection is done as follows:
|This page has been created by Sami Rautiainen.|
|Read the small print.||Last updated April 09, 2006.|