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System Specification for C65Fred BowenMarch 1, 1991

BITBit NameFunction
6RCVR EN 0= Receiver is disabled.

1= Receiver is Enabled. To provide noise immunity, the duration of a bit interval is segmented into 16 subintervals. This is also used to verify that a high to low transition (START bit) on the RXD line is valid (stays low) at the half point of a bit duration; if not valid, operation will not start.
If after an idle period, a high to low transition is detected on the RXD line and is verified to be low, the receiver will synchronized itself to the incoming character for the duration of the character. Received data is then sampled or latched in the center of a bit time to determine the value of the remaining bits. The LSB of the data is the leading bit received. Any unused high order register bits will be set "high". The receiver expects the data to have only one parity bit (when parity is enabled) and one stop bit.
At the end of the character reception, the receiver will check whether any errors have occured and will update the status register (URSR) accordingly. In addition, if no errors were encountered the receiver will load the contents of the shift register into the Receiver Data Register, eliminating parity and stop bits.

In synchronous mode, the receiver will reconfigure its Data Register and Shift Register so that only 8 data bits are always accepted on the RXD line. This mode only works if an external clock is applied on the PRC2 input line, which is used to shift the bits into the Receiver Shift Register. Data on the RXD is latched at the rising edge of the external clock applied in PRC2.

7XMITR EN 0= Transmitter is disabled.

1= Transmitter is Enabled. Transmitter will start operation once the microprocessor writes data to the transmitter data register (DREG), after which the Transmitter Shift Register is loaded and the start bit is placed on the TXD line. The LSB of the data is the leading bit being transmitted. The Transmitter is "doubled buffered" which means that the CPU can load a new character as soon as the previous one starts transmission.
This is indicated by the status register, bit 6 (URSR6-EMPTY Data Register), which when set, it indicates that the data register is ready to accept the next character. The character data format is illustrated by figure 1.3.

In synchronous mode, the transmitter will reconfigure its Data Register and Shift Register so that only 8 data bits are always transmitted on the TXD line, eliminating all parity and stop bits. The external clock output will be placed in the PRC2 line and will shift the data out of the transmitter shift register. Data on the TXD line will change on the falling edge of the PRC2 signal, the external clock.

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