|System Specification for C65||Fred Bowen||March 1, 1991|
0= Receiver is disabled.|
1= Receiver is Enabled. To provide noise immunity, the duration of a
bit interval is segmented into 16 subintervals. This is also used to
verify that a high to low transition (START bit) on the RXD line is
valid (stays low) at the half point of a bit duration; if not valid,
operation will not start.
In synchronous mode, the receiver will reconfigure its Data Register and Shift Register so that only 8 data bits are always accepted on the RXD line. This mode only works if an external clock is applied on the PRC2 input line, which is used to shift the bits into the Receiver Shift Register. Data on the RXD is latched at the rising edge of the external clock applied in PRC2.
0= Transmitter is disabled.|
1= Transmitter is Enabled. Transmitter will start operation once
the microprocessor writes data to the transmitter data register
(DREG), after which the Transmitter Shift Register is loaded and
the start bit is placed on the TXD line. The LSB of the data is
the leading bit being transmitted. The Transmitter is "doubled
buffered" which means that the CPU can load a new character as
soon as the previous one starts transmission.
In synchronous mode, the transmitter will reconfigure its Data Register and Shift Register so that only 8 data bits are always transmitted on the TXD line, eliminating all parity and stop bits. The external clock output will be placed in the PRC2 line and will shift the data out of the transmitter shift register. Data on the TXD line will change on the falling edge of the PRC2 signal, the external clock.
|This page has been created by Sami Rautiainen.|
|Read the small print.||Last updated July 28, 2002.|