2.3.6.2 UART Status Register (URSR)

BIT	Bit Name	Function
0	FULL	Receiver Data Register Full bit. This bit is forced to a low upon reset, or after the data register (DREG) is read. This bit is enabled only if the RCVER EN bit is set in the URCR register. The FULL bit is set when the character being received is transferred from the receiver shift register into the receiver data register. If an error is encountered in the character data, this bit will not he set and the proper error bit will be set in the URSR register.
1	OVR	Receiver Over-Run Error bit. This bit is cleared upon reset or after reading the receiver data register. This bit is set if the new received charater is attempted to be transferred from the receiver shift register before reading the last character from the data register. Therefore, the last-character is preserved in the data register while the new received character is lost.
2	PRTY	Receiver Parity Error bit. This bit is cleared upon reset or after reading the receiver data register. The PRTY bit will be set when a parity error is detected on the received character, provided the PARITY EN bit is set and receiver is running asynchronously.
3	FRME	Receiver Frame Error bit. This bit is cleared upon reset or after reading the receiver data register. The FRME bit is set whenever the received character contains a low in the first stop-bit slot.
4	IDLE	Receiver Idle bit. When this bit is written to a "high", the status register bits 0-3 are disabled until the receiver detects 10 consecutive marks, highs, on the RXD line, at which time the IDLE bit is cleared. This bit is also cleared upon reset. This bit allows the microprocessor, or any external microprocessor device, to ignore the transmission of a character until the start of the next character.
5	ENDT	Transmitter End of Transmission bit. This bit is cleared upon reset or whenever data is written sinto the transmitter data register, DREG. Setting this bit would disable the Transmitter Empty bit, EMPTY, until device completes transmission.