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System Specification for C65Fred BowenMarch 1, 1991

2.4.3 CSG 4567 Operation

The 4567 accesses two 8-bit memory blocks, which are up to 64K each, via two 8-bit bidirectional busses. These are D0-D7 and E0-E7. The D0-D7 bus is common with the CPU chip, ROM, SID, and the expansion port, and is used for system memory and bitplanes. The E0-E7 port is only conneted to RAM. This RAM is used for COLOR RAM, attribute RAM, system memory, and bitplanes.

To access these RAMsp the 4567 has two multiplexed address busses. These are MA0-MA7, and MBS-MB7. Lines MA0-MA4 are common to both 64K banks of RAM, but MA5-MA7 go only to bank A, and MB5-MB7 go only to bank B.

There are four types of DMA accesses which the 4567 can perform. Remember that RAS* is asserted on every memory clock cycle. These are...

modeoperationCASA*CASB*ROM*
1.4567 reading both banks.XX 
2.4567 reading bank "A"X  
3.4567 reading ROM  X
4.4567 doing refresh.   

There are six types of CPU routings to RAM and peripheral devices that are handled by the 4567.

modeoperationCASA*CASB*ROM*
2.CPU reading bank "A".X  
3.CPU reading bank "B". X 
4.CPU writing bank "A".X  
5.CPU writing bank "B". X 
6.CPU reading ROM   X
7.CPU accessing 1/01, 1/02, SID, ROMR, ROML    

There are four basic data routings through the 4567 chip. Three internal signals rout the data busses. WTREG (write 4567 register) enables routing the external D0-D7 bus to the internal register data bus. It is normally a logic 1. When it is brought low, the internal bus disconnects, and the D0-D7 bus output drivers turn on. This is for CPU-reads of 4567 registers or "B" bank RAM.

DBMEM (read "B" bank memory) routs the E0-E7 data bus to the inputs of the D0-D7 bus.output drivers when at logic level 1. This is for CPU reads of "B" bank RAM. When 0, (normal) the internal register data bus is routed to the D0-D7 bus output driver inputs, instead. WTBMEM (write B" bank memory) turns on the E0-E7 bus drivers which directly routs the D0-D7 data bus to the E0-E7 bus when 1. This is for LPU writes to the "B" bank RAM. When 0, (normal) the E0-E7 bus is input only.

modeoperationWtregRdBmemWtBmem
1.CPU write 4567 register, CPU access external, 4567 DMA, etc100 (default)
2.CPU read 4567 register000
3.CPU read B RAM010
4.CPU write B RAM101



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