THE OFFICIAL A2620 MEMORY RELOCATION HACK by Dave Haynie The A2620 is a basic synchronous 68020 system (as described above) running at 14.3 MHz. The A2620 supports math coprocessors up at up to 25MHz with the proper crystal, as well as up to 4 megabytes of 32 bit-wide DRAM. There is one feature available for special purpose use that isn't documented in the User's Manual. Normally, the 32 bit wide memory of the A2620 is autoconfigured memory, residing at the first autoconfiguration address assigned by the system (currently, $00200000). As a result of this memory being autoconfigured, it uses up part of the available reserved configuration space, as one might expect. With a modified PAL, it's possible to move this 2 or 4 megs of memory out of autoconfig, and as a result, 68000 addressable address space. This has the advantage of allowing the modified system to support around 13 megabytes of memory, though at a loss of DMA access to the 32 bit wide memory managed by the A2620. The A2620 derives its main addressing logic from the U305 PAL. This device compares a latched autoconfig address to the actual MMU address to decide is any memory access is taking place, and if so, which 2 meg bank that access is in. The selection function for the relocated RAM here is quite simple; all I have to do is act on memory accesses in the first 2 or 4 megs of the second 16 meg chunk of memory (given by A24 = 1). The MMU is kind enough to hide any CPU space addresses from us (Coprocessors in a 68020 system are on the logical bus), and other A2620 logic will hide any cycle with MEMSEL asserted from the external A2000 bus. In order to make this change somewhat reversible without actually having to remove PALs all the time, I've built a selection function that's keyed of the CONFIGURED signal in the A2620. If the NORAM jumper is installed, the autoconfig register won't be seen by the system, and the RAM will be located at $1000000. If the NORAM jumper isn't installed, normal configuration will take place. This configuration does count on the board being located at $0200000, as the current 1.3 OS does things (the original U305 does a complete autoconfiguration in the prescribed manner). -------- THIS PAL REPLACES A2620 PAL U305 on the A2620 PARTNO Replaces 390290-01 ; NAME U305 ; DATE May 28, 1989 ; REV 1 ; DESIGNER Haynie ; COMPANY Commodore ; ASSEMBLY 312828 ; LOCATION U305 ; /******************************************************************/ /* */ /* 68020 MMU RAM address decode, Tristate generation and ABR */ /* generation with special DRAM relocation. */ /* */ /******************************************************************/ /* Allowable Target Device Types: 20L8B */ /******************************************************************/ /* Free Pins: NONE */ /******************************************************************/ /* HISTORY */ /* DBH May 28: Version to support A24 for special */ /* addressing feature. */ /******************************************************************/ /** Inputs **/ PIN 4 = !BEER ; /* Amiga2000's Bus Error Signal */ PIN 5 = CONFIGED ; /* RAM configuration register is valid */ PIN 6 = !RAMSIZ ; /* RAM size, 2Megs or 4Megs */ PIN [7..9] = [A23..21] ; /* Address bits A23-21 */ PIN 10 = !BGACK ; /* Buss grant acknowledge from the '020 */ PIN 11 = !BOSS ; /* We are the boss of the bus */ PIN 13 = !RESET ; /* The system reset line */ PIN 14 = !AAS ; /* The amiga address strobe */ PIN 20 = MODE68K ; /* Make the 68000 the boss, fatally */ PIN 23 = !AS ; /* The '851 address strobe */ PIN 17 = A24 ; /* Address bit 24 */ /** Outputs **/ PIN 15 = !MEMSEL ; /* Memory select output */ PIN 16 = !BERR ; /* System Bus Error Signal */ PIN 21 = ABR ; /* Amiga bus request output */ PIN 22 = !TRISTATE ; /* Tristate all amiga bus lines */ PIN 18 = !BANK ; /* Which DRAM bank to access? */ PIN 19 = !DMAMEM ; /* Memory select for DMA */ /** Declarations and Intermediate Variable Definitions **/ field addr = [A24..21] ; /* 68851 address */ /* This equation indicates a valid memory access for the on-board RAM, either 2 meg or 4 meg versions. Note that the addresses are hard wired; if software tries to configure the board anywhere but at $0200000, it won't go there. If the memory's in autoconfig space, I make it wrap like a normal A2620's memory would. */ access = addr:[11fffff..1000000] & !CONFIGED # addr:[13fffff..1200000] & !CONFIGED & RAMSIZ # addr:[03fffff..0200000] & CONFIGED # addr:[05fffff..0400000] & CONFIGED & RAMSIZ # addr:[13fffff..1200000] & CONFIGED # addr:[15fffff..1400000] & CONFIGED & RAMSIZ; /** Logic Equations **/ /* The DRAM Bank logic; bank is asserted for the second bank of system memory. */ BANK = access & A21 & RAMSIZ & !CONFIGED # access & !A21 & RAMSIZ & CONFIGED; /* This DRAM memory select looks for a valid address access, valid addresses, and a valid configuration. We also have to make sure we're not in 68000 mode, where A24 will be invalid. */ MEMSEL = access & AS & !MODE68K; MEMSEL.OE = !BGACK; DMAMEM = access & AAS & CONFIGED; DMAMEM.OE = BGACK; /* We want tristate when we're not BOSS, or when we are BOSS but we're being DMAed. */ TRISTATE = !BOSS # (BOSS & BGACK); /* When we're first up after a global reset, we want to request the bus from the 68000. However, if we're in 68K mode, we don't want to request the bus. */ ABR = (!RESET & AAS & !BOSS & !MODE68K) # (!RESET & ABR & !BOSS & !MODE68K); /* Bus error from the A2000 should be seen by the 68020, but not the other way around, or autoconfig devices will get messed up. */ BERR = BEER ; BERR.OE = BEER ; -------- The proper way to link the memory into the system with this setup will be to "AddMem 01000000 011fffff" for a 2 meg system, or "AddMem 01000000 013ffffff" for a 4 meg system. The A2620 ROMs can apparently handle this case, but it hasn't been throughly tested.