PARTNO XXXXX ; NAME U600; DATE March 13, 1989; REV 3; DESIGNER Haynie ; COMPANY Commodore ; ASSEMBLY 312828 ; LOCATION U600; /************************************************************************/ /* */ /* A2630 RAS and burst generation machine */ /* */ /************************************************************************/ /* Allowable Target Device Types: 20R4-10 */ /************************************************************************/ /* Free Pins: NONE */ /************************************************************************/ /* HISTORY */ /* DBH Mar 8: New for A2630R5, based on U600 for Rev 4. */ /* DBH Mar 9: Fixed DMA bug. */ /* DBH Mar 13: Tuned DMA access as much as possible. */ /************************************************************************/ /** Inputs **/ PIN 2 = !ASDELAY ; /* AS plus arbitration delay */ PIN 3 = !AS ; /* 68030 address strobe */ PIN 4 = !AAS ; /* 68000 address strobe */ PIN 5 = !BGACK ; /* Bus grant acknowledge */ PIN 6 = !EXTERN ; /* EXTERN qualifier for specials */ PIN 7 = !MEMSEL ; /* The CPU is accessing our RAM */ PIN 8 = !REFACK ; /* It's a refresh cycle */ PIN 9 = !REFRAS ; /* RAS for refresh */ PIN 10 = !CHARGE ; /* RAS Precharge wait */ PIN 11 = !DMADELAY ; /* Don't start a DMA memory cycle. */ PIN 14 = !ROFF ; /* RAS off qualifier */ PIN 23 = !DSACKDLY ; /* Delay for starting DSACKs */ /** Outputs **/ PIN 22 = !DSACK0 ; /* Cycle terminator. */ PIN 21 = !RAS ; /* Unbuffered RAS */ PIN 19 = !AASQ ; /* AAS sampled by !CPUCLK */ PIN 15 = !DSACK1 ; /* Cycle terminator. */ /** Used internally */ PIN 18 = !AAS40 ; /* AASQ + Tclk */ PIN 17 = !AAS80 ; /* AAS40 + Tclk */ /** Declarations and Intermediate Variable Definitions **/ /* The standard qualification for a CPU memory cycle. We have to wait until refresh is arbitrated, and make sure we're selected and it's not an external cycle. */ cpucycle = !BGACK & !REFACK & MEMSEL & ASDELAY & AS & !EXTERN; cpudtack = cpucycle & DSACKDLY; /* The standard qualification for a DMA memory cycle. This is much the same as the CPU cycle, only it obeys the 68000 comparible signals instead of 68030 signals. The DMA cycle can DTACK early, since we know the minimum clock period is more than the DRAM access time. */ dmaaccess = BGACK & !REFACK & MEMSEL & AAS; dmadtack = dmaaccess & AAS80; dmacycle = dmaaccess & AAS40 & !DMADELAY; /* This indicates when a cycle is complete. */ cycledone = cpudtack # dmadtack; /** Logic Equations related to the refresh arbitration logic **/ /* These next lines make us delayed and synchronized versions of the 68000 compatible address strobe, used to handle refresh arbitration. */ AASQ.D = BGACK & AAS; AAS40.D = BGACK & AASQ; AAS80.D = BGACK & AAS40; /* This is the basic RAS enable. If it's a refresh cycle, we just go ahead. If it's the start of a standard CPU cycle, we wait until we're done charging, and then go. We continue until switched off by ROFF and the end of the cycle. If it's a DMA cycle, we go on ahead, since the time between DMA cycles is enough to assure Trp. */ RAS = cpucycle & !CHARGE # cpucycle & RAS & !ROFF # dmacycle # REFRAS; /* These are the cycle termination signals. They're really both the same, and both driven, indicating that we are, in fact, a 32 bit wide port. They go hi-Z when we're not selecting memory, so that other DSACK sources (FPU and the slow bus stuff) can get their chance to terminate. */ DSACK0 = cycledone; DSACK0.OE = MEMSEL; DSACK1 = cycledone; DSACK1.OE = MEMSEL;