From redfield@crunch Tue Sep 22 14:35:56 1992 Received: by cbmvax.cbm.commodore.com (5.57/UUCP-Project/Commodore 2/8/91) id AA08401; Tue, 22 Sep 92 14:35:53 EDT Received: from sol.lsidesign by crunch.lsidesign (4.1/SMI-4.0) id AA10715; Tue, 22 Sep 92 14:35:52 EDT Date: Tue, 22 Sep 92 14:35:52 EDT From: redfield@crunch (Jim Redfield) Message-Id: <9209221835.AA10715@crunch.lsidesign> To: daveh@cbmvax Subject: Re: AAA Clock Info... In-Reply-To: Mail from 'daveh@cbmvax (Dave Haynie)' dated: Tue, 22 Sep 92 13:23:51 EDT Cc: redfield Status: R Dave, No sh*t!? Great! Who is it? PCLK and MCLK. The chips require that both these signals be CMOS levels, ie >4.5 volt logic high level and <.5 logic low level. Nominally, the chip threshold to these is 2.5 volts (internal switching will occur around this level), so duty cycle is spec'ed relative to that. On both signals, we need a 50/50 duty cycle plus or minus 3% (47/53 to 53/47). Rise and fall delays, measured from .5 to 4.5 (rise) and from 4.5 to .5 (fall): 6ns, 6ns. rise and fall times should be within 10% of being equal, example: 5.4ns, 6.6ns to 6.6ns, 5.4ns. If you sketch these out you'll see they look somewhat sinusoidal. We would'nt mind if the rise and fall times were quicker than the 6ns spec'ed above. Jim By the way, how's the PCB coming? Message 4: >From daveh@cbmvax Tue Sep 22 13:24:02 1992 Return-Path: Received: from cbmvax.cbm.commodore.com by crunch.lsidesign (4.1/SMI-4.0) id AA10266; Tue, 22 Sep 92 13:24:01 EDT Received: by cbmvax.cbm.commodore.com (5.57/UUCP-Project/Commodore 2/8/91) id AA03295; Tue, 22 Sep 92 13:23:51 EDT Date: Tue, 22 Sep 92 13:23:51 EDT From: daveh@cbmvax (Dave Haynie) Message-Id: <9209221723.AA03295@cbmvax.cbm.commodore.com> To: redfield@cbmvax Subject: AAA Clock Info... Status: R Jim- I've been talking to guy from one of these clock synthesizer companies who can apparently make us a specifically-for-AAA system clock generator that'll do everything we want in one chip. Toward this end, I need some duty cycle requirements for PCLK and MCLK (I put the '040 clocks in there too, but I have a spec for that already). -Dave From redfield@crunch Tue Sep 22 14:44:52 1992 Received: by cbmvax.cbm.commodore.com (5.57/UUCP-Project/Commodore 2/8/91) id AA08854; Tue, 22 Sep 92 14:44:50 EDT Received: from sol.lsidesign by crunch.lsidesign (4.1/SMI-4.0) id AA10788; Tue, 22 Sep 92 14:44:50 EDT Date: Tue, 22 Sep 92 14:44:50 EDT From: redfield@crunch (Jim Redfield) Message-Id: <9209221844.AA10788@crunch.lsidesign> To: daveh@cbmvax Subject: PCLK/MCLK spec's, try 2. Cc: redfield Status: RO Dave (Try this again) No sh*t!? Great! Who is it? PCLK and MCLK. The chips require that both these signals be CMOS levels, ie >4.5 volt logic high level and <.5 logic low level. Nominally, the chip threshold to these is 2.5 volts (internal switching will occur around this level), so duty cycle is spec'ed relative to that. On both signals, we need a 50/50 duty cycle plus or minus 3% (47/53 to 53/47). Rise and fall delays, measured from .5 to 4.5 (rise) and from 4.5 to .5 (fall): 6ns, 6ns. rise and fall times should be within 10% of being equal, example: 5.4ns, 6.0ns to 6.0ns, 5.4ns. If you sketch these out you'll see they look somewhat sinusoidal. We would'nt mind if the rise and fall times were quicker than the 6ns spec'ed above. Jim By the way, how's the PCB coming?