From redfield@sol Thu Mar 4 18:05:59 1993 Received: by cbmvax.cbm.commodore.com (5.57/UUCP-Project/Commodore - Server Version 01/25/93) id AA20454; Thu, 4 Mar 93 18:05:52 EST Date: Thu, 4 Mar 93 18:02:23 EST From: redfield@sol (Jim Redfield) Received: by sol (4.1/921209-Commodore Intl Services Corp) id AA02580; Thu, 4 Mar 93 18:02:23 EST Message-Id: <9303042302.AA02580@sol> To: daveh@cbmvax.cbm.commodore.com Subject: AAA regnames Status: R REGNAME.HR(10-Apr-92) Advanced AMIGA chip regname ------------------------------------------------- &=Register used by DMA channel only. %=Register used by DMA channel usually, processors sometimes. +=Address register pair. Low word uses DB1-DB15, High word DB0-DB4. ~=Address not writable by the Coprocessor unless COPCON bit 1 is set true. h=new for HiRes chip set A=ANDREA chip, M=Monica chip, P=Mary chip W=Write, R=Read, DR=DMA channel read. This is a DMA data transfer to RAM, from either the Disk or from the Blitter. PTL,PTH=20 bit word Pointer that addresses DMA data. Must be reloaded by a processor before use (Vertical blank for Bit Plane and Sprite pointers, and prior to starting the Blitter for Blitter pointers).(old chips- 18 bits) PTX=22 bit long word pointer that addresses DMA data. LCL,LCH=20 bit Location (word starting address) of DMA data. Used to automatically restart pointers, such as the Coprocessor program counter (during vertical blank), and the Audio sample counter (whenever the audio length count is finished) (Old chips- 18 bits) LCX=22 bit location (long word starting address of DMA data MOD=15 bit Modulo. A number that is automatically added to the memory address at the end of each line to generate the address for the beginning of the next line. This allows the Blitter (or the Display Window) to operate on (or display) a window of data that is smaller than the actual picture in memory. (memory map) Uses 15 bits, plus sign extend. =============================================================================== Old RGA Addresses _______________________________________________________________________________ NAME ADD R/W CHIP FUNCTION ---------------------------------------- BLTDDAT & ~000 DR A Blitter dest. early read (dummy address) DMACONR ~002 R A DMA control (and blitter status) read VPOSR ~004 R A Read Vert most sig. bits (and frame flop) VHPOSR ~006 R A Read Vert and horiz Position of beam DSKDATR & ~008 DR P Disk data early read (dummy address) JOY0DAT ~00A R P Joystick-mouse 0 data (vert,horiz) JOY1DAT ~00C R P Joystick-mouse 1 data (vert,horiz) CLXDAT ~00E R M Collision data reg.(Read and clear) ADKCONR ~010 R P Audio, disk control register read POT0DAT ~012 R P Pot counter pair 0 data (vert,horiz) POT1DAT ~014 R P Pot counter pair 1 data (vert,horiz) POTINP ~016 R P Pot pin data read SERDATR ~018 R P Serial Port Data and Status read DSKBYTR ~01A R P Disk Data byte and status read INTENAR ~01C R P Interrupt Enable bits Read INTREQR ~01E R P Interrupt Request bits read DSKPTH + ~020 W A Disk pointer (High 5 bits) DSKPTL + ~022 W A Disk pointer (Low 15 bits) DSKLEN ~024 W P Disk length DSKDAT & ~026 W P Disk DMA Data write REFPTR & ~028 W A Refresh pointer VPOSW ~02A W A Write Vert most sig. bits (and frame flop) VHPOSW ~02C W A Write Vert and horiz Position of beam COPCON ~02E W A Coprocessor control register (CDANG) SERDAT ~030 W P Serial Port Data and stop bits write SERPER ~032 W P Serial Port Period and control POTGO ~034 W P Pot count start,pot pin drive enable and data JOYTEST ~036 W P Write to all 4 Joystick-mouse counters at once. ~038 ~03A ~03C ~03E BLTCON0 ~040 W A Blitter control register 0 BLTCON1 ~042 W A Blitter control register 1 BLTAFWM ~044 W A Blitter first word mask for source A BLTALWM ~046 W A Blitter last word mask for source A BLTCPTH + ~048 W A Blitter Pointer to source C (High 5 bits) BLTCPTL + ~04A W A Blitter Pointer to source C (Low 15 bits) BLTBPTH + ~04C W A Blitter pointer to source B (High 5 bits) BLTBPTL + ~04E W A Blitter pointer to source B (Low 15 bits) BLTAPTH + ~050 W A Blitter Pointer to source A (High 5 bits) BLTAPTL + ~052 W A Blitter Pointer to source A (Low 15 bits) BLTDPTH + ~054 W A Blitter Pointer to destn. D (High 5 bits) BLTDPTL + ~056 W A Blitter Pointer to destn. D (Low 15 bits) BLTSIZE ~058 W A Blitter start and size (window width, height) BLTCON0L h ~05A W A Blitter control 0 lower 8 bits(minterms) BLTSIZV h ~05C W A Blitter V size (for 15 bit vert size) BLTSIZH h ~05E W A Blitter H size & start (for 11 bit H size) BLTCMOD ~060 W A Blitter Modulo for source C BLTBMOD ~062 W A Blitter Modulo for source B BLTAMOD ~064 W A Blitter Modulo for source A BLTDMOD ~066 W A Blitter Modulo for destn. D ~068 do not use ~06A do not use ~06C do not use ~06E do not use BLTCDAT & ~070 W A Blitter source C data reg BLTBDAT & ~072 W A Blitter source B data reg BLTADAT & ~074 W A Blitter source A data reg ~076 do not use ~078 do not use ~07A MONICAID h ~07C R M Chip Revision level for MONICA (video out chip) DSKSYNC ~07E W P Disk sync pattern register for disk read. COP1LCH + 080 W A Coprocessor first location reg (High 5 bits) COP1LCL + 082 W A Coprocessor first location reg. (Low 15 bits) COP2LCH + 084 W A Coprocessor second location reg. (High 5 bits) COP2LCL + 086 W A Coprocessor second location reg(Low 15 bits) COPJMP1 088 S A Coprocessor restart at first location COPJMP2 08A S A Coprocessor restart at second location COPINS 08C W A Coprocessor inst. fetch identify DIWSTRT 08E W A Display Window Start (upper left vert-hor pos) DIWSTOP 090 W A Display Window Stop (lower right vert-hor pos) DDFSTRT 092 W A Display bit plane data fetch start(hor pos) DDFSTOP 094 W A Display bit plane data fetch stop(hor pos) DMACON 096 W A P DMA control write(clear or set) CLXCON 098 W M Collision control INTENA 09A W P Interrupt Enable bits (clear or set bits) INTREQ 09C W P Interrupt Request bits (clear or set bits) ADKCON 09E W P Audio, Disk, UART, Control AUD0LCH + 0A0 W A Audio channel 0 location (High 5 bits) AUD0LCL + 0A2 W A Audio channel 0 location (Low 15 bits) AUD0LEN 0A4 W P Audio Channel 0 length AUD0PER 0A6 W P Audio channel 0 Period AUD0VOL 0A8 W P Audio Channel 0 Volume AUD0DAT % 0AA W P Audio channel 0 Data 0AC 0AE AUD1LCH + 0B0 W A Audio channel 1 location (High 5 bits) AUD1LCL + 0B2 W A Audio channel 1 location (Low 15 bits) AUD1LEN 0B4 W P Audio Channel 1 length AUD1PER 0B6 W P Audio channel 1 Period AUD1VOL 0B8 W P Audio Channel 1 Volume AUD1DAT % 0BA W P Audio channel 1 Data 0BC 0BE AUD2LCH + 0C0 W A Audio channel 2 location (High 5 bits) AUD2LCL + 0C2 W A Audio channel 2 location (Low 15 bits) AUD2LEN 0C4 W P Audio Channel 2 length AUD2PER 0C6 W P Audio channel 2 Period AUD2VOL 0C8 W P Audio Channel 2 Volume AUD2DAT % 0CA W P Audio channel 2 Data 0CC 0CE AUD3LCH + 0D0 W A Audio channel 3 location (High 5 bits) AUD3LCL + 0D2 W A Audio channel 3 location (Low 15 bits) AUD3LEN 0D4 W P Audio Channel 3 length AUD3PER 0D6 W P Audio channel 3 Period AUD3VOL 0D8 W P Audio Channel 3 Volume AUD3DAT % 0DA W P Audio channel 3 Data 0DC 0DE BPL1PTH + 0E0 W A Bit plane 1 pointer (High 5 bits) BPL1PTL + 0E2 W A Bit plane 1 pointer (Low 15 bits) BPL2PTH + 0E4 W A Bit plane 2 pointer (High 5 bits) BPL2PTL + 0E6 W A Bit plane 2 pointer (Low 15 bits) BPL3PTH + 0E8 W A Bit plane 3 pointer (High 5 bits) BPL3PTL + 0EA W A Bit plane 3 pointer (Low 15 bits) BPL4PTH + 0EC W A Bit plane 4 pointer (High 5 bits) BPL4PTL + 0EE W A Bit plane 4 pointer (Low 15 bits) BPL5PTH + 0F0 W A Bit plane 5 pointer (High 5 bits) BPL5PTL + 0F2 W A Bit plane 5 pointer (Low 15 bits) BPL6PTH + 0F4 W A Bit plane 6 pointer (High 5 bits) BPL6PTL + 0F6 W A Bit plane 6 pointer (Low 15 bits) BPLCON0 100 W A M Bit plane control register(misc control bits) BPLCON1 102 W M Bit plane control reg (scroll value PF1, PF2) BPLCON2 104 W M Bit plane control reg (priority control) BPLCON3 106 W M Bit plane control reg (enhanced features) BPL1MOD 108 W A Bit plane modulo (odd planes) BPL2MOD 10A W A Bit Plane modulo (even planes) BPLCON4 10C W M Bit plane control reg (enhanced features) 10E BPL1DAT & 110 W M Bit plane 1 data (Parallel to serial convert) BPL2DAT & 112 W M Bit plane 2 data (Parallel to serial convert) BPL3DAT & 114 W M Bit plane 3 data (Parallel to serial convert) BPL4DAT & 116 W M Bit plane 4 data (Parallel to serial convert) BPL5DAT & 118 W M Bit plane 5 data (Parallel to serial convert) BPL6DAT & 11A W M Bit plane 6 data (Parallel to serial convert) 11C 11E SPR0PTH + 120 W A Sprite 0 pointer (High 5 bits) SPR0PTL + 122 W A Sprite 0 pointer (Low 15 bits) SPR1PTH + 124 W A Sprite 1 pointer (High 5 bits) SPR1PTL + 126 W A Sprite 1 pointer (Low 15 bits) SPR2PTH + 128 W A Sprite 2 pointer (High 5 bits) SPR2PTL + 12A W A Sprite 2 pointer (Low 15 bits) SPR3PTH + 12C W A Sprite 3 pointer (High 5 bits) SPR3PTL + 12E W A Sprite 3 pointer (Low 15 bits) SPR4PTH + 130 W A Sprite 4 pointer (High 5 bits) SPR4PTL + 132 W A Sprite 4 pointer (Low 15 bits) SPR5PTH + 134 W A Sprite 5 pointer (High 5 bits) SPR5PTL + 136 W A Sprite 5 pointer (Low 15 bits) SPR6PTH + 138 W A Sprite 6 pointer (High 5 bits) SPR6PTL + 13A W A Sprite 6 pointer (Low 15 bits) SPR7PTH + 13C W A Sprite 7 pointer (High 5 bits) SPR7PTL + 13E W A Sprite 7 pointer (Low 15 bits) SPR0POS % 140 W A M Sprite 0 Vert-Horiz start position data SPR0CTL % 142 W A M Sprite 0 position and control data SPR0DATA & 144 W M Sprite 0 image data register A SPR0DATB & 146 W M Sprite 0 image data register B SPR1POS % 148 W A M Sprite 1 Vert-Horiz start position data SPR1CTL % 14A W A M Sprite 1 position and control data SPR1DATA & 14C W M Sprite 1 image data register A SPR1DATB & 14E W M Sprite 1 image data register B SPR2POS % 150 W A M Sprite 2 Vert-Horiz start position data SPR2CTL % 152 W A M Sprite 2 position and control data SPR2DATA & 154 W M Sprite 2 image data register A SPR2DATB & 156 W M Sprite 2 image data register B SPR3POS % 158 W A M Sprite 3 Vert-Horiz start position data SPR3CTL % 15A W A M Sprite 3 position and control data SPR3DATA & 15C W M Sprite 3 image data register A SPR3DATB & 15E W M Sprite 3 image data register B SPR4POS % 160 W A M Sprite 4 Vert-Horiz start position data SPR4CTL % 162 W A M Sprite 4 position and control data SPR4DATA & 164 W M Sprite 4 image data register A SPR4DATB & 166 W M Sprite 4 image data register B SPR5POS % 168 W A M Sprite 5 Vert-Horiz start position data SPR5CTL % 16A W A M Sprite 5 position and control data SPR5DATA & 16C W M Sprite 5 image data register A SPR5DATB & 16E W M Sprite 5 image data register B SPR6POS % 170 W A M Sprite 6 Vert-Horiz start position data SPR6CTL % 172 W A M Sprite 6 position and control data SPR6DATA & 174 W M Sprite 6 image data register A SPR6DATB & 176 W M Sprite 6 image data register B SPR7POS % 178 W A M Sprite 7 Vert-Horiz start position data SPR7CTL % 17A W A M Sprite 7 position and control data SPR7DATA & 17C W M Sprite 7 image data register A SPR7DATB & 17E W M Sprite 7 image data register B COLOR00 180 W M Color table 00 COLOR01 182 W M Color table 01 COLOR02 184 W M Color table 02 COLOR03 186 W M Color table 03 COLOR04 188 W M Color table 04 COLOR05 18A W M Color table 05 COLOR06 18C W M Color table 06 COLOR07 18E W M Color table 07 COLOR08 190 W M Color table 08 COLOR09 192 W M Color table 09 COLOR10 194 W M Color table 10 COLOR11 196 W M Color table 11 COLOR12 198 W M Color table 12 COLOR13 19A W M Color table 13 COLOR14 19C W M Color table 14 COLOR15 19E W M Color table 15 COLOR16 1A0 W M Color table 16 COLOR17 1A2 W M Color table 17 COLOR18 1A4 W M Color table 18 COLOR19 1A6 W M Color table 19 COLOR20 1A8 W M Color table 20 COLOR21 1AA W M Color table 21 COLOR22 1AC W M Color table 22 COLOR23 1AE W M Color table 23 COLOR24 1B0 W M Color table 24 COLOR25 1B2 W M Color table 25 COLOR26 1B4 W M Color table 26 COLOR27 1B6 W M Color table 27 COLOR28 1B8 W M Color table 28 COLOR29 1BA W M Color table 29 COLOR30 1BC W M Color table 30 COLOR31 1BE W M Color table 31 HTOTAL h 1C0 W A Highest number count in horiz line (VARBEAMEN=1) HSSTOP h 1C2 W A Horiz line pos for HSYNC stop HBSTRT h 1C4 W A Horiz line pos for HBLANK start HBSTOP h 1C6 W A Horiz line pos for HBLANK stop VTOTAL h 1C8 W A Highest numbered Vertical line (VARBEAMEN=1) VSSTOP h 1CA W A Vert. line pos for VSYNC stop VBSTRT h 1CC W A Vert line for VBLANK start VBSTOP h 1CE W A Vert line for VBLANK stop 1D0 1D2 1D4 1D6 HHPOSW h 1D8 W A DUAL mode hires H beam counter write HHPOSR h 1DA R A DUAL mode hires H beam counter read BEAMCON0 h 1DC W A Beam counter control register(SHRES,UHRES,PAL) HSSTRT h 1DE W A Horizontal Sync start (VARHSY) VSSTRT h 1E0 W A Vertical Sync start (VARVSY) HCENTER h 1E2 W A Horizontal position for Vsync on interlace DIWHIGH h ~1E4 W A M Display window- upper bits for start,stop 1E6 1E8 1EA 1EC 1EE AUD4DAT n %1F0 W P Audio Channel 4 16 bit data register AUD5DAT n %1F2 W P Audio Channel 5 16 bit data register AUD6DAT n %1F4 W P Audio Channel 6 16 bit data register AUD7DAT n %1F6 W P Audio Channel 7 16 bit data register RESERVED 1F8-1FC NO-OP(NULL) 1FE Usually indicates refresh cycle, or processor RAM access cycles. =============================================================================== 32 Bit Control Registers _______________________________________________________________________________ NAME ADD R/W CHIP FUNCTION ---------------------------------------- AUDLEFTR ~200 R P Read left audio channel VHPOSRX ~204 R A Extended Read Vert and Hori Position of beam. DSKDATRX &~208 DR P Disk DMA Data read DMACONRX ~20C R A Extended DMA Control read ADKCONRX ~210 R P Audio, Disk, UART, Control read DSKBYTRX ~214 R P Disk DATA word and status read INTREQRX ~218 R P Interrupt Request bits (read) INTENARX ~21C R P Interrupt Enable bits (read) DSKPLLP ~220 W P Disk Phase Lock Loop Phase Adjust. DSKPLLF ~224 W P Disk Phase Lock Loop Frequency Adjust. DSKDATX &~228 W P Disk DMA Data write VHPOSWX ~22C W A Extended Write Vert and Hori Position of beam. DSKPLLR ~230 R P Disk Phase Lock Loop status read register(test). DSKPTX ~234 W A Extended Disk Pointer (address bits 23-0) BLTPATRNR ~238 R A Blitter line draw pattern read register. BLTLLENX ~23C R A Blitter line length read register. ~240 BLTPMSKX ~244 W A Plane Mask. ~248 BLTASRCPTX ~24C W A Bit Map A Pointer. BLTBSRCPTX ~250 W A Bit Map B Pointer. BLTDSRCPTX ~258 W A Bit Map D Pointer. BLTASRCWDX ~25C W A Bit Map A Width. BLTBSRCWDX ~260 W A Bit Map B Width. BLTDSRCWDX ~264 W A Bit Map D Width. BLTSIZEX ~268 W A Blit Size. BLTAORGX ~26C W A Blit A Origin. BLTBORGX ~270 W A Blit B Origin. BLTDORGX ~274 W A Blit D Origin. BLTFUNCX ~278 W A Blit Function and Start Register. DSKSYNCX ~27C W P Longword disk sync pattern for disk read. COP1LC 280 W A Extended coprocessor first location reg. COP2LC 284 W A Extended coprocessor second location reg. 288 ADKCONX 28C W P Audio, Disk, UART, Control write DMACONX 290 W A Extended DMA control write INTENAX 294 W P Interrupt Enable bits (clear or set) CLXCONX 298 W M Extended Collision Control INTREQX 29C W P Interrupt Request bits (clear or set) AUD0LCX 2A0 W P Extended Audio channel 0 backup pointer AUD0LENX 2A4 W P Extended Audio channel 0 length AUD0PERX 2A8 W P Extended Audio channel 0 period AUD0VOLX 2AC W P Extended Audio channel 0 volume AUD0DATX % 2B0 W P Extended Audio channel 0 data AUD0CTL 2B4 W P Audio channel 0 control bits AUD1LCX 2B8 W P Extended Audio channel 1 backup pointer AUD1LENX 2BC W P Extended Audio channel 1 length AUD1PERX 2C0 W P Extended Audio channel 1 period AUD1VOLX 2C4 W P Extended Audio channel 1 volume AUD1DATX % 2C8 W P Extended Audio channel 1 data AUD1CTL 2CC W P Audio channel 1 control bits AUD2LCX 2D0 W P Extended Audio channel 2 backup pointer AUD2LENX 2D4 W P Extended Audio channel 2 length AUD2PERX 2D8 W P Extended Audio channel 2 period AUD2VOLX 2DC W P Extended Audio channel 2 volume AUD2DATX % 2E0 W P Extended Audio channel 2 data AUD2CTL 2E4 W P Audio channel 2 control bits AUD3LCX 2E8 W P Extended Audio channel 3 backup pointer AUD3LENX 2EC W P Extended Audio channel 3 length AUD3PERX 2F0 W P Extended Audio channel 3 period AUD3VOLX 2F4 W P Extended Audio channel 3 volume AUD3DATX % 2F8 W P Extended Audio channel 3 data AUD3CTL 2FC W P Audio channel 3 control bits BPL1DATX & 300 W M Extended Bitplane data register 1 BPL2DATX & 304 W M Extended Bitplane data register 2 BPL3DATX & 308 W M Extended Bitplane data register 3 BPL4DATX & 30C W M Extended Bitplane data register 4 BPL5DATX & 310 W M Extended Bitplane data register 5 BPL6DATX & 314 W M Extended Bitplane data register 6 318 31C SPR0PTX 320 W A Extended SPRITE 0 pointer register SPR1PTX 324 W A Extended SPRITE 1 pointer register SPR2PTX 328 W A Extended SPRITE 2 pointer register SPR3PTX 32C W A Extended SPRITE 3 pointer register SPR4PTX 330 W A Extended SPRITE 4 pointer register SPR5PTX 334 W A Extended SPRITE 5 pointer register SPR6PTX 338 W A Extended SPRITE 6 pointer register SPR7PTX 33C W A Extended SPRITE 7 pointer register SPR0DATAX & 340 W M Extended Sprite 0 image data register B SPR0DATBX & 344 W M Extended Sprite 0 image data register A SPR1DATAX & 348 W M Extended Sprite 1 image data register B SPR1DATBX & 34C W M Extended Sprite 1 image data register A SPR2DATAX & 350 W M Extended Sprite 2 image data register B SPR2DATBX & 354 W M Extended Sprite 2 image data register A SPR3DATAX & 358 W M Extended Sprite 3 image data register B SPR3DATBX & 35C W M Extended Sprite 3 image data register A SPR4DATAX & 360 W M Extended Sprite 4 image data register B SPR4DATBX & 364 W M Extended Sprite 4 image data register A SPR5DATAX & 368 W M Extended Sprite 5 image data register B SPR5DATBX & 36C W M Extended Sprite 5 image data register A SPR6DATAX & 370 W M Extended Sprite 6 image data register B SPR6DATBX & 374 W M Extended Sprite 6 image data register A SPR7DATAX & 378 W M Extended Sprite 7 image data register B SPR7DATBX & 37C W M Extended Sprite 7 image data register A SPR0POSX % 380 W A M Extended Sprite 0 Vert start and stop position data SPR0CTLX % 384 W M Extended Sprite 0 position and control data SPR1POSX % 388 W A M Extended Sprite 1 Vert start and stop position data SPR1CTLX % 38C W M Extended Sprite 1 position and control data SPR2POSX % 390 W A M Extended Sprite 2 Vert start and stop position data SPR2CTLX % 394 W M Extended Sprite 2 position and control data SPR3POSX % 398 W A M Extended Sprite 3 Vert start and stop position data SPR3CTLX % 39C W M Extended Sprite 3 position and control data SPR4POSX % 3A0 W A M Extended Sprite 4 Vert start and stop position data SPR4CTLX % 3A4 W M Extended Sprite 4 position and control data SPR5POSX % 3A8 W A M Extended Sprite 5 Vert start and stop position data SPR5CTLX % 3AC W M Extended Sprite 5 position and control data SPR6POSX % 3B0 W A M Extended Sprite 6 Vert start and stop position data SPR6CTLX % 3B4 W M Extended Sprite 6 position and control data SPR7POSX % 3B8 W A M Extended Sprite 7 Vert start and stop position data SPR7CTLX % 3BC W M Extended Sprite 7 position and control data HTOTALX 3C0 W A Extended horiz line count register DIWSTRTX 3C4 W A M Extended Display Window Start DIWSTOPX 3C8 W A M Extended Display Window Stop HBSTOPX 3CC W A Extended horiz blank stop HBSTRTX 3D0 W A Extended horiz blank start HCENTERX 3D4 W A Extended horiz line center HSSTOPX 3D8 W A Extended horiz sync stop HSSTRTX 3DC W A Extended horiz sync start BPL1PTX 3E0 W A Extended Bitplane 1 pointer BPL2PTX 3E4 W A Extended Bitplane 2 pointer BPL3PTX 3E8 W A Extended Bitplane 3 pointer BPL4PTX 3EC W A Extended Bitplane 4 pointer BPL5PTX 3F0 W A Extended Bitplane 5 pointer BPL6PTX 3F4 W A Extended Bitplane 6 pointer 3F8 3FC RAMATRN ~400 R A RAM Bank Attributes read register COINTRER ~404 R A Coprocessor interrupt request/enable read register. PRITEST ~408 R A Read Processor and Blitter priority control bits. BLTROMD ~40C R A Blitter ROM data. AUDTST0R ~410 R P Read audio cycle addr, ctrl state, and data AUDTST1R ~414 R P Read audio cycle control and test control bits AUDRIGHTR ~418 R P Read right audio channel SERDATR2N ~41C R P Serial Port 2 Data and Status read AUDTST0W ~420 W P Write audio cycle addr, ctrl state, and data GENERALR ~424 R A General purpose register, read. VPPOSRN ~428 R A Read Primary vertical position of beam. BLITENRN ~42C R A Blitter Enable register read. PRISET ~430 W A Write Processor and Blitter priority control bits. BLITEN ~434 W A Blitter Enable register. AUDTST1W ~438 W P Write audio cycle control and test control bits BLTLCLPAX ~43C W A Blitter Clip Rectangle Coordinates, Source A. BLTLCLPBX ~440 W A Blitter Clip Rectangle Coordinates, Source B. BLTLCOLORX ~444 W A Blitter Line Color Register. BLTLPATRNX ~448 W A Blitter Line Pattern Register. BLTLPMSKX ~450 W A Blitter Line Plane Mask Register. BLTLMAPPTX ~454 W A Blitter Line Source Pointer Register. BLTLMAPWDX ~458 W A Blitter Line Width Register. BLTLEND1X ~45C W A Blitter Line End Point 1 Register. BLTLEND2X ~460 W A Blitter Line End Point 2 Register. BLTLFUNCX ~464 W A Blitter Line Function and Start Register. BLTADATX &~468 W A Blitter Source A Data Register. BLTBDATX &~46C W A Blitter Source B Data Register. BLTCDATX &~470 W A Blitter Source C Data Register. BLTDDATX &~474 DR A Blitter Source D Data Register. BLTEDATX &~478 DR A Blitter Source E Data Register. RAMATWN ~47C W A RAM Bank Attributes write register BLTTST 480 W A Blitter ROM test. SERDAT2N 484 W P Serial Port 2 Data and stop bits write MONITORID 488 R External Hardware Monitor ID. SERPERN 48C W P Serial Port 2 Period and control BPLOFFR 490 R M Bitplane and Sprite LUT Address Offset read reg CLXCONOEN 494 W M Chunky Pixel collision control; enable bits. CLXCONODN 498 W M Chunky Pixel collision control; match bits. MONTEST 49C W M MONICA test register. AUD4LCN 4A0 W P Extended Audio channel 4 backup pointer AUD4LENN 4A4 W P Extended Audio channel 4 length AUD4PERN 4A8 W P Extended Audio channel 4 period AUD4VOLN 4AC W P Extended Audio channel 4 volume AUD4DATN % 4B0 W P Extended Audio channel 4 data AUD4CTL 4B4 W P Audio channel 4 control bits AUD5LCN 4B8 W P Extended Audio channel 5 backup pointer AUD5LENN 4BC W P Extended Audio channel 5 length AUD5PERN 4C0 W P Extended Audio channel 5 period AUD5VOLN 4C4 W P Extended Audio channel 5 volume AUD5DATN % 4C8 W P Extended Audio channel 5 data AUD5CTL 4CC W P Audio channel 5 control bits AUD6LCN 4D0 W P Extended Audio channel 6 backup pointer AUD6LENN 4D4 W P Extended Audio channel 6 length AUD6PERN 4D8 W P Extended Audio channel 6 period AUD6VOLN 4DC W P Extended Audio channel 6 volume AUD6DATN % 4E0 W P Extended Audio channel 6 data AUD6CTL 4E4 W P Audio channel 6 control bits AUD7LCN 4E8 W P Extended Audio channel 7 backup pointer AUD7LENN 4EC W P Extended Audio channel 7 length AUD7PERN 4F0 W P Extended Audio channel 7 period AUD7VOLN 4F4 W P Extended Audio channel 7 volume AUD7DATN % 4F8 W P Extended Audio channel 7 data AUD7CTL 4FC W P Audio channel 7 control bits GRAPHICS & 500 W L Graphics fetch cycle BPLOFFN 504 W M Bitplane and Sprite offset register. BPL7DATN & 508 W M New Bit plane 7 data (Parallel to serial convert) BPL8DATN & 50C W M New Bit plane 8 data (Parallel to serial convert) BPL9DATN & 510 W M New Bit plane 9 data (Parallel to serial convert) BPL10DATN & 514 W M New Bit plane 10 data (Parallel to serial convert) BPL11DATN & 518 W M New Bit plane 11 data (Parallel to serial convert) BPL12DATN & 51C W M New Bit plane 12 data (Parallel to serial convert) BPL13DATN & 520 W M New Bit plane 13 data (Parallel to serial convert) BPL14DATN & 524 W M New Bit plane 14 data (Parallel to serial convert) BPL15DATN & 528 W M New Bit plane 15 data (Parallel to serial convert) BPL16DATN & 52C W M New Bit plane 16 data (Parallel to serial convert) BPLOVRDAT & 530 W M Overlay Bitplane data (Parallel to serial convert) COPWAIT 534 W A Coprocessor wait interrupt routine start address. COPJMP3 538 W A Coprocessor restart at third location. COPJMP4 53C W A Coprocessor restart at fourth location. COP3LC 540 W A Coprocessor third jump location register. COP4LC 544 W A Coprocessor fourth jump location register. COPBLITLC 548 W A Blitter Finished interrupt starting addr. COPRET 54C S A Coprocessor return from interrupt strobe. COINTREW 550 W A Coprocessor interrupt request/enable write reg. COPRETC 554 S A Coprocessor return from blitter interrupt strobe. 558 55C GENERALW 560 W A General purpose register, write. 564 BRSTSTRT 568 W A Burst start. BRSTSTOP 56C W A Burst stop. EQU1STOP 570 W A First equalization pulse stop position. EQU2STOP 574 W A Second equalization pulse stop position. SER1STOP 578 W A First serration pulse stop position. SER2STOP 57C W A Second serration pulse stop position. VEQUSTOP 580 W A Vertical equalization stop line. CLCNTR 584 W A Composite Line Center. MLSYNC 588 W A Mid Line Sync. 58C DSKCRCI 590 W P Initial CRC value register. DSKGAP 594 W P Disk gap timer register. DSKLENN 598 W A P New mode length register. DSKHDPT 59C W A New disk DMA header pointer. DSKBKPT 5A0 W A New disk DMA backup pointer. DSKTST 5A4 W P Disk test register. 5A8 5AC 5B0 5B4 5B8 5BC 5C0 5C4 5C8 5CC 5D0 5D4 BPL7PT 5D8 W A New bit plane 7 pointer BPL8PT 5DC W A New bit plane 8 pointer BPL9PT 5E0 W A New bit plane 9 pointer BPL10PT 5E4 W A New bit plane 10 pointer BPL117PT 5E8 W A New bit plane 11 pointer BPL12PT 5EC W A New bit plane 12 pointer BPL13PT 5F0 W A New bit plane 13 pointer BPL14PT 5F4 W A New bit plane 14 pointer BPL15PT 5F8 W A New bit plane 15 pointer BPL16PT 5FC W A New bit plane 16 pointer 600- 7FC reserved. COLORnRX 800- R M Extended color register read addresses. thru BFC COLORnWX C00- W M Extended color register write addresses. thru FFC