PARTNO xxxxxxxx-xx; NAME U701; DATE January 30, 1992; REV 3 ; DESIGNER Haynie ; COMPANY Commodore ; ASSEMBLY A30000 ; LOCATION U701 ; /************************************************************************/ /* */ /* A3000 Interrupt mixing & latch, primary bus arbitration */ /* */ /************************************************************************/ /* Allowable Target Device Types: 16R4A */ /************************************************************************/ /* Clock: 7Mhz */ /************************************************************************/ /* Free Pins: 14(Q) */ /************************************************************************/ /* HISTORY */ /* DBH Apr 5: Completely new. */ /* DBH Dec 6: Added bus arbiter stuff. */ /* DBH Jan 30: Changes to run without motherboard CPU. */ /************************************************************************/ /** Inputs **/ PIN 2 = !CIPL0 ; /* Chip conditioned interrupts */ PIN 3 = !CIPL1 ; PIN 4 = !CIPL2 ; PIN 5 = !PINT1 ; /* Bus interrupts */ PIN 6 = !PINT4 ; PIN 7 = !PINT5 ; PIN 8 = !PINT7 ; PIN 9 = !INTENB ; /* Interrupt enable */ PIN 18 = !CBR ; /* Coprocessor slot bus request */ PIN 19 = !BOSS ; /* Coprocessor slot owns system */ /** Outputs **/ PIN 17 = !IPL0 ; /* CPU interrupts */ PIN 16 = !IPL1 ; PIN 15 = !IPL2 ; PIN 12 = !BG ; /* Bus grant out to Buster */ /** Bidirectionals **/ PIN 13 = !BG30 ; /* Bus Grant from 68030 */ /** Declarations and Intermediate Variable Definitions **/ /* This sets up the different interrupt levels, as they may be generated by Paula or the discrete interrupt lines. These terms handle the prioritization. */ level0 = !CIPL2 & !CIPL1 & !CIPL0 & !(PINT1 # PINT4 # PINT5 # PINT7); level1 = !CIPL2 & !CIPL1 & CIPL0 & !(PINT4 # PINT5 # PINT7) # PINT1 & !(PINT4 # PINT5 # PINT7); level2 = !CIPL2 & CIPL1 & !CIPL0 & !(PINT4 # PINT5 # PINT7); level3 = !CIPL2 & CIPL1 & CIPL0 & !(PINT4 # PINT5 # PINT7); level4 = CIPL2 & !CIPL1 & !CIPL0 & !(PINT5 # PINT7) # PINT4 & !(PINT5 # PINT7); level5 = CIPL2 & !CIPL1 & CIPL0 & !PINT7 # PINT5 & !PINT7; level6 = CIPL2 & CIPL1 & !CIPL0 & !PINT7; level7 = CIPL2 & CIPL1 & CIPL0 # PINT7 ; /** Logic Equations **/ /* Here we drive the interrupt bits. */ IPL2.D = level7 & INTENB # level6 & INTENB # level5 & INTENB # level4 & INTENB ; IPL1.D = level7 & INTENB # level6 & INTENB # level3 & INTENB # level2 & INTENB ; IPL0.D = level7 & INTENB # level5 & INTENB # level3 & INTENB # level1 & INTENB ; /* This is the bus grant stuff. When the A3000 has a processor on the motherboard, the equations looks like this: BG = BG30 & !CBR; BG.OE = !BOSS; The idea behind the coprocessor slot is to turn arbitration over to the coprocessor device if its present. This means we can't clog the '030's arbitration mechanism. The system and coprocessor each have their own bus request (BR*, CBR*) and bus grant acknowledge (BGACK*, BOSS*), either of which have the desired effect on the motherboard '030. This gives the coprocessor a separate channel, so it can get rid of the '030 and still arbitrate the system requests. The grant line, however, isn't an input, but in fact an output to the system. So it must really be multiplexed rather than shared -- the '030's BG* goes to the system when it's in charge, the coprocessor's BG* when it's in charge. The coprocessor is clever enough to keep it's BG* in tristate until it owns the system, but the '030 doesn't know about all this. So this PAL isolates the system BG* from the '030's BG* when the coprocessor is in charge. In order to prevent the system from seeing any grants while the coprocessor is acquiring the bus, BG* only flows from BG30* when no coprocessor request is happening. That's a nice story, and all well and good until this PAL came along. It proports to let you run your A3000 with no motherboard processor, while staying compatible with existing coprocessor protocols. First, let's look at the coprocessor protocol. The coprocessor takes over by asserting CBR* and waiting for BG30* to be returned to it. Then it asserts BOSS* and negates CBR*, which results in BG30* being negated. It now owns the bus and directly deals with BR*, BG*, and BGACK* to the system just like any '030 equivalent. Basically, without a motherboard processor, a coprocessor device can just get up and go, not permission required. However, to fake out coprocessor devices that deal with normal A3000s, the best thing to do is make BG30* respond immediately to CBR*, thereby making the coprocessor think some kind of motherboard processor is actually present. */ BG30 = CBR; /* This has no bearing on devices that run in sharing mode (the C= '040 board is the only one of these I know about). There would be a problem with that mechanism here. Basically, these devices time multiplex the system BR* line with the Buster chip. The problem is that when such a device asserts BR*, there's not going to be a motherboard processor around to assert BG* for them. We could do it here if this PAL got BR* routed to it (we already have BG*). That shouldn't be a problem in a new system, since all these PINT* lines are obselete. BG = BR; */