The only known problem with the A4000 system is the behavior of the A4000's
Fast RAM as a Zorro III bus master.  This observed problem only pertains to
Zorro III bus reads from Fast RAM, not writes.  

The Zorro III bus specifies a minimum delay between DTACK* asserted and FCS* 
negated of 10ns, but it does not specifiy a maximum delay.  So, in theory, 
any slave device should be able to stand some reasonably long DTACK* to FCS* 
delay.  We don't specify a maximum, though we probably will in the future.


The A4000 design sets a practial limit now anyway. If the DTACK* to FCS* delay
is much beyond 80ns, the A4000 memory controller will start a new memory cycle 
to the exact same address.  At some point, roughly 120ns-160ns, the A4000 
memory controller will generate another STERM*, which gets translated into 
another Zorro III DTACK*.  Since STERM* to DTACK* is latched, this doesn't
create any problem as long as the Zorro III cycle is still going.  However, if
the Zorro III cycle terminates at just the right point, STERM* will be active
long enough to cause a false DTACK* near the start of the next Zorro III
cycle.  Therefore, for proper Zorro III DMA from A4000 Fast RAM, FCS* should
be cut off as soon after DTACK* as practical, ideally no longer than 40ns
after DTACK* is received.

					-Dave