CUPL 4.0a Serial# MD-40A-8380 Device g22v10 Library DLIB-h-26-1 Created Mon Apr 12 14:46:32 1993 Name U205 Partno 391581-02 Revision 5 Date April 1, 1993 Designer Dave Haynie Company Commodore Assembly A4091 Location West Chester *QP24 *QF5892 *G0 *F0 *L00000 11111111111111111111111111111011 *L00032 11111111111111111111111111111111 *L00064 11111111111111111111111111111111 *L00096 10111111101111111111111111101111 *L00128 11111111111101111111111111111111 *L00160 11111101111111110000000000000000 *L00416 00000000000000000000000011111111 *L00448 11111111111111111111111111111111 *L00480 11111111111101111111111111111111 *L00512 11111101111111111111111110111111 *L00544 10111111111111111110111111111111 *L00576 11101011111111111111111111111110 *L00608 11111111000000000000000000000000 *L00896 00000000000000000000000000001111 *L00928 11111111111111111111111111111111 *L00960 11111111110101111011011101111111 *L00992 11110111111011111111111101111011 *L01024 11110111011111111111111011111111 *L01056 11111011011111110111101111111111 *L01088 11011111111111111011011101110111 *L01120 11111111111111011111111100000000 *L01472 00000000000000000000000011111111 *L01504 11111111111111111111111111111111 *L01536 11111111011110110111011111111110 *L01568 11111110111111111111101101110111 *L01600 01111111111011111101111111111111 *L01632 11111111110101111111111111111111 *L01664 11111111000000000000000000000000 *L02144 00000000000011111111111111111111 *L02176 11111111111111111111111111110111 *L02208 10111111011101111111111111101111 *L02240 11111111101101111111011110111111 *L02272 11111101111111110000000000000000 *L02880 00000000000000000000000011111111 *L02912 11111111111111111111111111111111 *L02944 11111111011110111111011110111111 *L02976 11111110111111111111101101111111 *L03008 01110111111111111101111111110000 *L03648 00001111101111111111011111111111 *L03680 01111111111111111111101111110111 *L03712 01111011111111111111111101111111 *L03744 10111111011101111111101111111111 *L03776 11111111111110111111011101111111 *L03808 11111110111111111111111110111111 *L03840 01110111111111111111111111111110 *L03872 11111011111101110111111111111111 *L03904 11111011111111111011111101110111 *L03936 11111111111101111111111111111011 *L03968 11110111011111111110111111111111 *L04000 11110000000000000000000000000000 *L05792 00000000000000000000011101010101 *L05824 01000000010001001100000011001011 *L05856 01001000110000011100101011001000 *L05888 1100 *CA529 *F659 PARTNO U205 ; NAME U205 ; DATE April 1, 1993 ; REV 5 ; DESIGNER Dave Haynie ; COMPANY Commodore ; ASSEMBLY A4091 ; LOCATION West Chester ; DEVICE g22v10 ; /************************************************************************/ /* */ /* A4091 Buffer and termination control. */ /* */ /* This device manages data buffer direction, enable, and latch */ /* functions, address buffer enable, and slave cycle termination. */ /* */ /************************************************************************/ /* */ /* DEVICE DATA: */ /* */ /* Device: 22V10-15 */ /* Clock: CLK (25MHz) */ /* Unused: 16(I/O) */ /* */ /************************************************************************/ /* */ /* REVISION HISTORY: */ /* */ /* DBH Jul 8: Original version. */ /* DBH Oct 26: Extended data latching function. */ /* DBH Nov 2: Modified DTACK again for fast SCSI slave cycle */ /* termination. */ /* DBH Nov 19: Changed DBOE for self-reference support. */ /* DBH Mar 30: Added NOZ3 term for quick Zorro III disconnect, */ /* to eliminate the multiple A4091 problem. */ /* DBH Apr 1: Some more NOZ3-related tweaks. */ /************************************************************************/ /** INPUTS: **/ PIN 1 = CLK ; /* 25MHz system clock. */ PIN 2 = !SLAVE ; /* Board select. */ PIN 3 = !MYBUS ; /* The A4091 has the bus. */ PIN 4 = DOE ; /* Data phase on Zorro III. */ PIN 5 = FCS ; /* Z3 full cycle strobe. */ PIN 6 = READ ; /* The Zorro III read cycle. */ PIN 7 = !SLACK ; /* The NCR 53C710 slave acknowledge. */ PIN 8 = !NOZ3 ; /* Get off the Z3 bus? */ PIN 9 = INTREG ; /* Interrupt register access. */ PIN 10 = !INTVEC ; /* Interrupt vector access. */ PIN 11 = !CFGOUT ; /* Configuration chain output. */ PIN 13 = !NACK ; /* Network chip acknowledge. */ PIN 14 = !MTCR ; /* Zorro III burst strobe. */ PIN 15 = !MASTER ; /* SCSI chip owns the A3090 bus. */ PIN 16 = !SID ; /* SCSI ID. */ /** OUTPUTS: **/ PIN 18 = !D2Z ; /* Data is transferred to Zorro III bus. */ PIN 19 = !Z2D ; /* Data is transferred from Zorro III bus. */ PIN 20 = DBLT ; /* Data is latched. */ PIN 21 = !DBOE ; /* Data transfer enable. */ PIN 22 = !ABOEL ; /* Low order address transfer enable. */ PIN 23 = !ABOEH ; /* High order address transfer enable. */ /** BIDIRECTIONALS: **/ PIN 17 = !DTACK ; /* Zorro III termination. */ /** LOGICAL TERMS: **/ /* It takes both MYBUS and MASTER to fully qualify a cycle. If MYBUS is asserted but master not, we're in the process of bus arbitration. If MASTER is asserted but not MYBUS, the SCSI chip is master of the A4091 bus and waiting for a grant to the Zorro bus. In both of these cases, as little as possible should be done. */ mastercyc = MYBUS & MASTER; slavecyc = !MYBUS & !MASTER; /** OUTPUT TERMS: **/ /* This is the data output enable control. When data buffers are pointed toward the board, they can turn on early in the cycle. This is a write for slave access, a read for DMA access. When the data buffers are pointed out toward the bus, the have to wait until DOE to turn on; this is a slave read or DMA write. When the board responds to itself, the buffers are left off. If the NOZ3 signal is asserted on a write (eg, master driving the Zorro III bus), DBOE must be negated immediately. */ DBOE = slavecyc & SLAVE & !READ & FCS # slavecyc & SLAVE & READ & FCS & DOE # mastercyc & !SLAVE & !READ & FCS & DOE & !ABOEH & !NOZ3 # mastercyc & !SLAVE & READ & FCS; /* The data buffer direction calculations are very simple. The data to Zorro III connection is made for slave reads or DMA writes. The Zorro III to data bus connection is made for slave writes or DMA reads. */ D2Z = slavecyc & READ & FCS & SLAVE # mastercyc & !READ & FCS & !SLAVE; Z2D = slavecyc & !READ & FCS & SLAVE # mastercyc & READ & FCS & !SLAVE; /* For either kind of access, data is latched when DTACK is asserted and we're in data time. Data is held through the end of the cycle. */ DBLT = slavecyc & FCS & DTACK & DOE & SLAVE # mastercyc & FCS & DTACK & DOE & !SLAVE # DBLT & FCS; /* The address buffer controls. I want addresses going in unless the SCSI device has been granted the A3090 bus. If so, addresses only go out when the A3090 has been granted the Zorro III bus. High order addresses also go off quickly after FCS is asserted. */ ABOEL.D = slavecyc # mastercyc & !FCS # mastercyc & FCS & ABOEL; ABOEL.AR = NOZ3; ABOEH.D = slavecyc # mastercyc & !FCS; ABOEH.AR = NOZ3; /* The board needs to generate a DTACK here for slave accesses. Most of the slave terminations are very simple, since they're either based on a termination signal (SLACK for SCSI, NACK for net or ROM) or they're instant (interrupt vector R/W). During configuration, any write should also be instantly terminated, that would be a configuration register write (reads are governed by ROM access). */ DTACK = SLAVE & FCS & DOE & SLACK # SLAVE & FCS & DOE & INTREG # SLAVE & FCS & DOE & INTVEC # SLAVE & FCS & DOE & SID # SLAVE & FCS & DOE & NACK # SLAVE & FCS & DOE & !CFGOUT & !READ # SLAVE & FCS & DOE & DTACK; DTACK.OE = SLAVE & FCS & !NOZ3;   CUPL 4.0a Serial# MD-40A-8380 Device g22v10 Library DLIB-h-26-1 Created Mon Apr 12 14:46:48 1993 Name U305 Partno 391586-02 Revision 6 Date April 5, 1993 Designer Dave Haynie Company Commodore Assembly A3090 Location West Chester *QP24 *QF5892 *G0 *F0 *L00000 11111111011111111111111111111111 *L00032 11111111111100000000000000000000 *L00416 00000000000000000000000011011011 *L00448 11111111111111111111111111111111 *L00480 11111111111111110111111111111111 *L00512 11111111111111111111111111111111 *L00544 11111111111111111111111110100000 *L00896 00000000000000000000000000001101 *L00928 10111111111111111111111111111111 *L00960 11111111111111111111011111111111 *L00992 11111111111111111111111111111111 *L01024 11111111111111111111111111111001 *L01056 11111111111111111111101111111111 *L01088 11111111101111111111111111110111 *L01120 11111111111111111111101100000000 *L01472 00000000000000000000000011011011 *L01504 11111111111111111111111111111111 *L01536 11111111111111110111111111111111 *L01568 11111111111111111111111111111111 *L01600 11111111111111111111111101101111 *L01632 11111111111111111011111111111111 *L01664 11111001111111111111111101110111 *L01696 11111111111111111011111111111111 *L01728 11111011101111111111111111111011 *L02144 00000000000011011011111111111111 *L02176 11111111111111111111111111111111 *L02208 11110111111111111111111111111111 *L02240 11111111111111111111111111111111 *L02272 11111111111101011111111111111111 *L02304 01111111111111111111111101111111 *L02336 11111111111110111011111111111111 *L02368 11111111111111111111111101110111 *L02400 11111111111111111101000000000000 *L03648 00001111111111111111111111111111 *L03680 11111111111111111111101111111111 *L03712 11111111111011111111111111111111 *L03744 10111011111111111101111111101111 *L03776 11111111000000000000000000000000 *L04288 00000000000000000000000011111111 *L04320 11111111111111111111111111111111 *L04352 11111111111110111111111111111110 *L04384 11011111111111111111101110111111 *L04416 11111110111111111111111111111111 *L04448 01111011111111111111111111011111 *L04480 11111111111101110111111111111110 *L04512 11111111111111111111000000000000 *L05792 00000000000000000101010101010011 *L05824 00000000010001001100000011001011 *L05856 01000110110000011100101011001000 *L05888 1100 *C9CE4 *D79A PARTNO U305 ; NAME U305 ; DATE April 5, 1993 ; REV 6 ; DESIGNER Dave Haynie ; COMPANY Commodore ; ASSEMBLY A3090 ; LOCATION West Chester ; DEVICE g22v10 ; /************************************************************************/ /* */ /* A3090 SCSI Master Interface */ /* */ /* This device provides most of the Zorro III bus master interface */ /* to the NCR 53C710. */ /* */ /************************************************************************/ /* */ /* DEVICE DATA: */ /* */ /* Device: 22V10-10 */ /* Clock: CLK (25MHz) */ /* Unused: 9(I),10(I),14(I/O),15(I/),17(I/O) */ /* */ /************************************************************************/ /* */ /* REVISION HISTORY: */ /* */ /* DBH Jul 9: Original version. */ /* DBH Oct 26: Changes made to speed up Zorro III version of */ /* the FCS signal. */ /* DBH Nov 2: Hold onto BFCS until AS goes away for slaves. */ /* DBH Nov 17: ASQ shutoff based on !AS to prevent FCS echo. */ /* DBH Nov 19: Eliminate A3 passthrough, part of the self- */ /* reference fix. */ /* DBH Apr 1: Added the MASTER signal to prevent bogus A4091 */ /* activities when SCSI has the A4091 bus but not */ /* the Zorro III bus. */ /* DBH Apr 5: When things lined up just right, we missed */ /* the start of the new AS* cycle. Now it's */ /* interlocked with the end of the FCS cycle. */ /* COMPILE -M3 */ /************************************************************************/ /** INPUTS: **/ PIN 1 = CLK ; /* 33MHz system clock. */ PIN 2 = !MYBUS ; /* A3090 has the Zorro III bus. */ PIN 3 = !AS ; /* SCSI address strobe. */ PIN 4 = READ ; /* The Zorro III read cycle. */ PIN 5 = SIZ1 ; /* SCSI transfer size. */ PIN 6 = SIZ0 ; PIN 7 = !NOZ3 ; /* Zorro III bus cutoff */ PIN 8 = !MTCR ; /* Zorro III multiple transfer strobe. */ PIN 10 = MASTER ; /* SCSI chip owns A4091 bus. */ PIN 11 = A1 ; /* SCSI sizing addresses. */ PIN 13 = A0 ; PIN 18 = !EFCS ; /* Zorro III cycle strobe. */ PIN 23 = DOE ; /* Zorro III data ouput enable. */ /** OUTPUTS: **/ PIN 16 = BFCS ; /* Buffered cycle strobe. */ PIN 17 = !ASQ ; /* Qualified version of the SCSI AS* */ PIN 19 = !DS0 ; /* Zorro III data strobes. */ PIN 20 = !DS1 ; PIN 21 = !DS2 ; PIN 22 = !DS3 ; /** BIDIRECTIONALS: **/ /** OUTPUT TERMS: **/ /* The buffered FCS depends on the mode. In non-DMA modes, it's simply based on the expansion FCS, as long as a SCSI-chip cycle isn't present (that would indicate DMA awaiting a grant). In DMA, the expansion FCS starts a cycle, but it can go away before the A4091 SCSI chip cycle is complete, so a latching term is added. */ /* With MASTER, I could interlock differently. BFCS = EFCS & !MASTER & !MYBUS # EFCS & MASTER & MYBUS # BFCS & AS & ASQ & MYBUS # BFCS & AS & !MYBUS;*/ BFCS = EFCS & !MYBUS & !AS # BFCS & !MYBUS & AS # EFCS & MYBUS & AS # BFCS & MYBUS & AS & ASQ; /* A Zorro III cycle is started based on the start of a SCSI cycle and the A3090's ownership of the Zorro III bus. This is a qualifier for that start. */ ASQ.D = AS & !BFCS & !EFCS & MYBUS # ASQ & MYBUS; ASQ.AR = !AS; /* The data strobes are based on the low order address and size input from the SCSI chip. We don't turn these on until the A3090 is bus master and it's data time. The conversions are standard '030 style conversions. */ DS3 = READ # !A1 & !A0; DS2 = READ # !A1 & !SIZ0 # !A1 & A0 # !A1 & SIZ1; DS1 = READ # !A1 & !SIZ1 & !SIZ0 # !A1 & SIZ1 & SIZ0 # !A1 & A0 & !SIZ0 # A1 & !A0; DS0 = READ # A0 & SIZ1 & SIZ0 # !SIZ1 & !SIZ0 # A1 & A0 # A1 & SIZ1; [DS3..0].OE = MYBUS & DOE;   CUPL 4.0a Serial# MD-40A-8380 Device g22v10 Library DLIB-h-26-1 Created Mon Apr 12 14:47:07 1993 Name U306 Partno 391587-02 Revision 5 Date March 29, 1993 Designer Dave Haynie Company Commodore Assembly A3090 Location West Chester *QP24 *QF5892 *G0 *F0 *L00000 11111111101111111111111111111111 *L00032 11111111111100000000000000000000 *L00416 00000000000000000000000011111111 *L00448 11111111111111111111111111111111 *L00480 11110111101110111111111111111111 *L00512 11111111010110111111101011111111 *L00544 11111111111111111111010110110000 *L01472 00000000000000000000000011111111 *L01504 11111111111111111111111111111111 *L01536 11111111111101111110111011111111 *L01568 11111111011111111111111101111111 *L01600 11101111111111111111011011110000 *L02144 00000000000011111011111111111111 *L02176 11111111111111111111111111111011 *L02208 01111111111111111111111111100111 *L02240 11111111111101111111111011111111 *L02272 11111111011111110000000000000000 *L02880 00000000000000000000000011111010 *L02912 11111111111111111111111111111111 *L02944 11111111101011111111111111101111 *L02976 11111111011111111011101011111111 *L03008 11111111111111111111011111110000 *L03648 00001111111111111111111111111111 *L03680 11111111111111111111100101111111 *L03712 11111111111111111111111111111111 *L03744 11111111111111111111111111111111 *L03776 10111111000000000000000000000000 *L04288 00000000000000000000000011111111 *L04320 11111111111111111111111111111111 *L04352 11111111011101111111111111111111 *L04384 11011111011011111111111101111110 *L04416 11111111111111011111011011110000 *L04864 00000000000000000000111111111111 *L04896 11111111111111111111111111111111 *L04928 11111011011111111101111111111111 *L04960 11111111111111111111011111111111 *L04992 11111111111111101111111100000000 *L05344 00000000000000000000000011111111 *L05376 11111111111111111111111111111111 *L05408 11111111111101111111111111111111 *L05440 11011111011011111111111101111111 *L05472 11111111101111111111011111110000 *L05792 00000000000000000101010010010100 *L05824 00010100110000001100101101001110 *L05856 11000001110010101100100011001001 *L05888 1100 *C8382 *B85E PARTNO U306; NAME U306 ; DATE March 29, 1993 ; REV 5 ; DESIGNER Dave Haynie ; COMPANY Commodore ; ASSEMBLY A3090 ; LOCATION West Chester ; DEVICE g22v10 ; /************************************************************************/ /* */ /* A3090 SCSI Burst Control */ /* */ /* This device manages burst and some other bits of NCR 53C710 to */ /* Zorro III bus translation. */ /* */ /************************************************************************/ /* */ /* DEVICE DATA: */ /* */ /* Device: 22V10-10 */ /* Clock: !CLK (33MHz) */ /* Unused: 13(I) */ /* */ /************************************************************************/ /* */ /* REVISION HISTORY: */ /* */ /* DBH Jul 9: Original version. */ /* DBH Oct 26: The expansion FCS is now generated here. */ /* DBH Oct 26: Reworked DTSYNC and STERM to free up AR for */ /* use EFCS. */ /* DBH Oct 26: Find the missing DTACK. Fix to correct this. */ /* DBH Oct 28: Changes here for a different FCS/DTACK strategy */ /* that makes the FCS shutoff delay independent of */ /* A3090 DTACK sampling. */ /* DBH Oct 29: Changed above to also insure STERM is generated */ /* in slave mode, even at 25MHz. */ /* DBH Mar 29: Stolen the unused BURST pin for NOZ3. This */ /* is asserted to get the A4091 off the Zorro III */ /* bus quickly, even when its local FCS may still */ /* be active. This is designed to fix the */ /* multiple A4091 problem. */ /************************************************************************/ /** INPUTS: **/ PIN 1 = !CLK ; /* 33MHz system clock. */ PIN 2 = !MYBUS ; /* SCSI owns the Zorro III bus. */ PIN 3 = BFCS ; /* A3090 local Zorro III cycle strobe. */ PIN 4 = !MTACK ; /* Zorro III slave burst strobe. */ PIN 5 = !CBREQ ; /* SCSI burst request. */ PIN 6 = !SCSI ; /* SCSI slave chip select. */ PIN 7 = !EDTACK ; /* Zorro III data acknowledge, on bus. */ PIN 8 = !ABOEH ; /* High order address buffer enable. */ PIN 9 = !BERR ; /* Zorro III bus error. */ PIN 10 = !RST ; /* Zorro III reset. */ PIN 11 = !ASQ ; /* Clocked and qualified SCSI strobe. */ /** OUTPUTS: **/ PIN 14 = !BDTACK ; /* Zorro III data acknowledge, buffered. */ PIN 16 = !STERM ; /* SCSI termination. */ PIN 17 = !NOZ3 ; /* Stop driving Zorro III! */ PIN 18 = !EFCS ; /* Zorro III cycle strobe for DMA. */ PIN 19 = DOE ; /* Zorro III data ouput enable. */ PIN 21 = !MTCR ; /* Zorro III multiple transfer strobe. */ PIN 23 = !CBACK ; /* SCSI burst acknowledge. */ /** USED INTERNALLY: **/ PIN 15 = !DCNT ; /* State bit for Zorro III stuff. */ PIN 20 = !DTSYNC ; /* Synchronizer for DTACK->STERM. */ PIN 22 = !CYCZ3 ; /* On-bus Zorro III cycle. */ /** OUTPUT TERMS: **/ /* The Zorro III cycle starts on-bus as soon as it's certain to be a real cycle that's starting. If just starting, the buffered FCS isn't asserted but ASQ is. Once on, it stays on until a DTACK is properly noticed. */ CYCZ3 = !RST & MYBUS & !BFCS & ASQ & !BDTACK & !CLK # !RST & MYBUS & CYCZ3 & ASQ & !BDTACK; /* The master-mode FCS is asserted onto the bus once we have determined a real out-to-bus Zorro III cycle should take place. This wasn't originally clocked out, but I got nervous about ABOEH setup. */ EFCS = CLK & MYBUS & CYCZ3 & !RST # EFCS & MYBUS & CYCZ3 & !RST; EFCS.OE = MYBUS & CYCZ3; /* Get off the Zorro III bus right after the EFCS cycle ends, hold it until the local cycle ends. */ NOZ3 = MYBUS & BFCS & !CYCZ3 # RST; /* The data output enable has to wait until a safe "data phase". This is guaranteed to be two clocks after FCS falls. DCNT is used to time this from cycle's start. */ DOE.D = BFCS & !RST & !DOE & MYBUS & DCNT # BFCS & !RST & DOE; DOE.OE = MYBUS; /* This is a count phase from FCS, to ensure proper DOE assertion. */ DCNT.D = BFCS & !DOE & !DCNT & MYBUS # BFCS & DCNT; /* This signal samples a termination signal. It used to sample EDTACK, but the quick turnoff of EFCS means that EDTACK may be gone before our sampling edge comes around. Instead, the state where EFCS is negated but BFCS is asserted indicates that the EFCS logic has detected EDTACK. */ DTSYNC.D = BFCS & !RST & DOE & BDTACK # BFCS & !RST & DOE & DTSYNC; DTSYNC.AR = !BFCS; /* The SCSI termination is based on a synchronized DTACK. I synchronize DTACK for either slave or master cycle, since the NCR 53C710 wants the effect of SLACK (which makes a DTACK on slave to SCSI cycles) reflected on STERM to actually end the cycle. */ STERM.D = !RST & MYBUS & BFCS & DTSYNC & !STERM & BDTACK # !RST & !MYBUS & BFCS & BDTACK & !STERM; STERM.AR = !BFCS; /* We _never_ issue a CBACK, since BURST isn't supported. */ CBACK = 'b'0; CBACK.OE = 'b'0; /* We _never_ issue an MTCR, since BURST isn't supported. */ MTCR = 'b'0; MTCR.OE = 'b'0; /* The DTACK line is buffered into the rest of the board. It actually latches the EDTACK line in various ways, since EDTACK isn't necessarily going to hang around long enough to be sampled. */ BDTACK = !RST & BFCS & EDTACK # !RST & BFCS & BDTACK & !STERM;