2031 HP CIRCUIT THEORY

Microprocessor/VIA Logic

U3J is a VIA, Versatile Interface Adapter. During a write operation, the microprocessor passes the data to be recorded to Port A of U3J. The data is loaded into the shift register U3L. It is converted from parallel to serial data and output to the write amplifier circuit. During a read operation, serial data is received from the read amplifier circuit.

The stepper motor is controlled by two outputs on port B of U3J, STP0, and STP1. A binary four count is developed from these two lines by U1P, see Sheet 4. The MTR output on pin 12 controls the spindle motor, refer to the motor control schematic on page 18. The write protect switch, WPS, is monitored at pin 14 of U3J and the red activity LED is controlled at pin 13.

Varying Frequency Clock

The DS0 and DS1 outputs of U3J, pins 15 and 16, are input at pins 1 and 15 of U5M U5M is a programmable counter (÷ 16, ÷ 15, ÷ 14, ÷ 13) that outputs a varying frequency clock used to compensate for the difference in recording area/sector for sectors on inner tracks (Trks 1,2,3) as compared to sectors on out most tracks (Trks 33,34,35). The area/sector for inner tracks is less than the area/sector for outer tracks, so the recording clock frequency is increased when writing on inner tracks to keep the flux density constant. This clock output is on pin 12 of U5M and is used to clock the data from the read amplifier circuits.

Read/Write Control Logic

During a write operation, U3L converts parallel data into serial data. The output on pin 9 is input to 'NAND' gate U6M pin 5. U6M outputs the serial data on pin 6 at the clock rate determined by the input signal on pin 4. The output clocks the D flip flop U5N (see Sheet 4). The outputs of U5N, Q and Q, drive the write amplifiers.

During a read operation, data from the read amplifiers is applied to the CLR input of counter U2N. The outputs, C and D, are shaped by the 'NOR' gate U2M. U2M. outputs the serial data on pin 1, then it is converted to parallel data by U2K. The output of U2K is latched by U3K. The serial bits are counted by U5L. When 8 bits have been counted, U6K pin 6 goes "low", U5J pin 6 goes "high", and U6K pin 8 goes "low" indicating byte is ready to be read by the processor. U2L monitors the parallel output of U2K. When all 8 bits are "1", the output pin 9 goes "low" indicating a sync bit has been read.