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Clock (PHI2)  —  The PHI2 clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system data bus.

Chip Select (CS)  —  The CS input controls the activity of the 8520. A low level on CS while PHI2 is high causes the device to respond to signals on the R/W and address (RS) lines. A high on CS prevents these lines from controlling the 8520. The CS line is normally activated (low) at PHI2 by the appropriate address combination.

Read/Write (R/W)  —  The R/W signal is normally supplied by the microprocessor and controls the direction of data transfers of the 8520. A high on R/W indicates a read (data transfer out of the 8520), while a low indicates a write (data transfer into the 8520).

Address Bus (RS3-RS0)  —  The address inputs select the internal registers as described by the Register Map.

Data Bus (DB7-DB0)  —  The eight bit data bus transfers information between the 8520 and the system data bus. These pins are high impedance inputs unless CS is low and RW and PHI2 are high, to read the device. During this read, the data bus output buffers are enabled, driving the data from the selected register onto the system data bus.

Interrupt Request (IRQ)  —  IRQ is an open drain output normally connected to the processor interrupt input. An external pullup resistor holds the signal high, allowing multiple IRQ-outputs to be connected together. The IRQ output is normally off (high impedance) and is activated low as indicated in the functional description.

Reset (RES)  —  A low on the RES pin resets all internal registers. The port pins are set as inputs and port registers to zero (although a read of the ports will return all highs because of passive pullups). The timer control registers are set to zero and the timer latches to all ones. All other registers are reset to zero.

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This page has been created by Frank Kontros.
Last updated May 14th, 1999.