[Prev] [Next] [Contents] [Commodore] [New] [Search] [Home]


[Cassette interface schematic]
The Cassette Interface Circuits.
U7 is a 6510 microprocessor. One of the features of the 6510 is a built in parallel I/O port (P0-P5). P3 - P5 control most of the cassette interface circuitry. P3 pin p6 of U7 outputs the write data signal to connector CN3 on pins E and 5. P4 is an input that senses the play switch depressed on the cassette deck. P5 is on output that controls the cassette motor. When P5 goes "low", Q2 cuts off, CR2 regulates Vb of Q1 at 7.5 volts, this forward biases Q1 and Q3, passing current through the cassette motor coil. U1 is a Complex Interface Adapter (CIA). Parallel ports, serial outputs, and Timers are standard features of the CIA. Read data enters on pins D, 4 of CN3. U1 accepts the read data signal on the FLAG input pin 24.
[Prev] [Next] [Contents] [Commodore] [New] [Search] [Home]
This page has been created by Sami Rautiainen.
Read the small print. Last updated September 05, 2020.