2031 HP CIRCUIT THEORY

Microprocessor Control of RAM and ROM

U5F and U5H are 8192 x 8 bit ROMS that store the Disk Operating System (DOS). U5F resides at memory locations $C000-$DFFF. U5H resides at memory locations $E000-$FFFF. U5J and U5K decode the addresses output from the microprocessor when selecting these ROMS.

U3B, C, D and E are 2114 Static RAMS (24 x 4). They reside at memory locations $0000-$07FF. This memory is used for processor stack operations, general processor housekeeping, user program storage, and 4 temporary buffer areas. U5J, U5K, and U6J decode the addresses output from the processor when selecting RAM. U6J also decodes the address selection of the VlAs, U3J and U3H.

The Clock Circuit

The clock circuit outputs a 16 MHz clock signal at U4C pin 11. This is input to U4D on pin 5. U4D is configured as a - 16 frequency divider. The output of U4D pin 7 is a 1 MHz clock signal used as the system clock (Phase 0) for the microprocessor. The 16 MHz clock signal is also used for the varying frequency clock circuit, see Sheet 1.

The Power Supply

THE CHASSIS: When the switch is closed, the AC voltage input is applied to the primary winding of the transformer. Circuit protection is provided by a .5 amp fuse. The transformer steps down the AC input voltage into two smaller AC voltages: One secondary output (approx. 16VRMS) is applied at connector P3 pins 1 and 4, the other secondary output (approx. 9VRMS) is applied at P3 pins 2 and 3.

THE PCB: The 16VRMS AC applied between pins 1 and 4 is converted to DC by the full wave bridge rectifier CR1. The DC output of CR1. is regulated at + 12VDC by VR2. High frequency filtering is provided by C6, low frequency filtering by C2 and C4. The 9VRMS AC applied between pins 2 and 3 is converted to DC by the full wave bridge rectifier CR2. The DC output is regulated at +5VDC by VR1. High frequency filtering is provided by C5, low frequency filtering by C1 and C3.