U1P converts STP0 and STP1 into outputs that create a binary four count. The outputs Y0, Y1, Y2, and Y3 from U1P are inverted by U1N. The outputs of the inverters drive the transistors of U1L. The current output from these transistors drive the individual phase coils in the stepper motor and return to the 12VDC supply. CR6-CR9 suppress the CEMF developed by the motor coils.
When data is recorded on the disk, a "1" bit is represented on the disk by a change in direction of magnetic flux, caused by a change in direction of current passed through the R/W coil in the R/W head. When a "0" bit is to be recorded, no change in current flow direction occurs, causing the direction of the magnetic flux to remain the same on the disk.
When data is being read from the disk, CEMF is induced into the R/W coil by the magnetic fields on the disk, causing current flow which is detected by the read amplifiers. Current flow through the R/W coil will forward bias either CR12 or CR14, depending on the direction. Q1 and CR16 must be forward biased. The first amplifier, U5R, senses this current flow from the R/W coil on one of the inputs and amplifies it. L2, L3, L4, L5 and C39 act as a low pass filter, suppressing noise on the amplified output. U3R is a differential amplifier which amplifies the difference of the two input signals from the filter section. U2R is a peak detector. The output of U2R will pulse "high" when a "1" is read. This signal is the reconstruction of data recorded. The time domain filter, U3N, times out when a "1" bit has been read, so unwanted "1" bits are not added to the actual data. The one shot, U3N, generates the correct data pulse width.
During a write operation, pin 4 of U6N must be "high". This forward biases Q1 and CR16. If pin 5 of U5N, Q, goes "low", Q4 and CR1 5 become forward biased, passing current flow through R/W 1. If _Q goes "low", Q5 and CR13 become forward biased, passing current flow through R/W 2.
When a write operation occurs, the ERASE coil is energized by forward biasing CR11. This demagnetizes the outer edges of the track, preventing data on one track from bleeding into the next track.
This circuit prevents erroneous data from being written on the disk during power up/down sequences. During a power up, the 12VDC supply is not applied to the R/W coils and amplifier circuits before the processor has control of the logic. During a power down, the 12VDC supply is removed from the R/W coils and amplifier circuits before the processor loses control of the logic.
Q3 acts as a series pass transistor biased to regulate the 12VF output to the R/W coils and amplifier circuits. Q2 is a feedback amplifier monitoring the 5VDC supply. CR1 7 develops a precise reference voltage for Q2. L1 and C45 delay the 12VDC supply.
|This page has been created by Sami Rautiainen.|
|Read the small print.||Last updated November 17, 1998.|