WD1770 FLOPPY DISK CONTROLLER (CONTINUED)

Arithmetic/Logic Unit (ALU)  —  The ALU is a serial comparator, incrementator, and decrementator, and is used for register modification and comparisions with the disk recorded ID field.

Timing and Control  —  All computer and Floppy Disk interface controls are generated through this logic. The internal device timing is generated from an external crystal clock. The WD1770 has two different modes of operation according to the state of . When =0, double density (MFM) is enabled. When =1, single density is enabled.

AM Detector  —  The address mark detector detects ID, data and index address marks during read and write operations.

Data Separator  —  A digital data separator, consisting of a right shift register and data window detection logic, provides read data and a recovery clock to the AM detector.

PROCESSOR INTERFACE

The interface to the processor is accomplished through the eight Data Access Lines (DAL) and associated control signals. The DAL are used to transfer Data Status, and Control words out of, or into the WD1770. The DAL are three state buffers that are enabled as output drivers when Chip Select () and =1 are active or act as input receivers when and =0 are active.

When transfer of data with the Floppy Disk Controller is required by the host processor, the device address is decoded and is made low. The address bits A1 and A0, combined with the signal , during a Read operation or Write operation are interpreted as selecting the following registers:

A1	A0	Read (=1)	Write (=0)
0 0 1 1	0 1 0 1	Status Register Track Register Sector Register Data Register	Command Register Track Register Sector Register Data Register

During Direct Memory Access (DMA) types of data transfers between the Data Register of the WD1770 and the processor, the Data Request (DRQ) output is used in Data Transfer control. This signal also appears as status bit 1 during Read and Write operations.

On Disk Read operations, the Data Request is activated (set high) when an assembled serial input byte is transferred in parallel to the Data Register. This bit is cleared when the Data Register is read by the processor. If the Data Register is read after one or more characters are lost, by having new data transferred into the register prior to processor readout, the Lost Data bit is set in the Status Register. The Read operation continues until the end of sector is reached.

On Disk Write operations, the Data Request is activated when the Data Register transfers its contents to the Data Shift Register, and requires a new data byte. It is reset when the Data Register is loaded with new data by the processor. If new data is not loaded at the time the next serial byte is required by the Floppy Disk, a byte of zeroes is written on the diskette and the Lost Data is set in the Status Register.

At the completion of every command, an INTRQ is generated. INTRQ is reset by either reading the status register, or by loading the command register with a new command. In addition, INTRQ is generated if a Force Interrupt command condition is met.

The WD1770 has two modes of operation according to the state (Pin 26). When =1, single density is selected. In either case, the CLK input (Pin 18) is at 8 MHZ.

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