System Specification for C65: C65 System Hardware - The CSG 4510 Microcontroller Chip (cont.)

System Specification for C65

Fred Bowen

March 1, 1991

DB7-DB0 34 thru 41 I/O DO-D7 form an 8 bit bi-directional data bus for data exchanges to and from the internal CPU (the 65CE02) and the device internal registers. it is also used to communicate with external peripheral devices. The output buffers are capable of driving two standard TTL loads and 55pf.

R/W 43 I/O This signal is generated by the CPU to control the direction of data transfers on the data bus. This line is high except when the CPU is writing to memory, an internal I/O register or an external device. When the AEC Or DMA/ signal is low, the R/W becomes tri-state.

RH0 44 IN This clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system data bus. Two internal clocks are generated by the device; phase two (PH2) is in phase with RH0 and phase one (PH1) is 180 degrees out of phase with RH0.

PC/ 53 OUT This output line is a strobe signal and is Centronics interface compatible. The signal goes low following a read or write access of PORT D.

PRD0-PRD7
PRB0-PRB7
PRA0-PRA7 45 thru 52
54 thru 61
62 thru 61 I/O
I/O
I/O These are three 8-bit ports with each of their lines having a passive pull-up (min. 3K ohm) as well as active pull-up and pull-down transistors. Each individual port line may be programmed to be either input or output.

PRC2 70 I/O This line corresponds to PORT C, bit 2. It has passive pull-up (min. 3k ohm) as well as active pull-up and pull- down transistors. The line can be configured as input or output. PRC2 becomes the external shift register clock when the UART is configured to operate in the synchronous mode, otherwise PRC2 operates as normal.

PRC3 71 OUT This signal is an open drain output with a. passive pull-up (1K ohm min). It corresponds to bit 3 of PORT C. When this port bit is set as an input, the PRC3 line is driven low; reading the port bit will give a high. If configured as an output, reading this port bit will not give the status of the PRC3 line but the value previously written on the PORT C data reg. bit 3.

PRC46 72 I/O This is an open drain bi-directional signal with a passive pull-up (1K ohm min). Bit 6 of PORT C is always configured as an input; the bit will give the status of the PRC46 line anytime the the port is read, regardless of what is written in the data direction register.
If bit 4 of PORT C is set as an input, the PRC46 line will be pulled low; reading the port bit will give a high. If bit 4 is configured as an output, PRC46 will be pulled low if hit 4 in the port data register is high, otherwise the PRC46 line will float to a high.

This page has been created by Sami Rautiainen.
Read the small print.	Last updated August 10, 2001.

DB7-DB0	34 thru 41	I/O	DO-D7 form an 8 bit bi-directional data bus for data exchanges to and from the internal CPU (the 65CE02) and the device internal registers. it is also used to communicate with external peripheral devices. The output buffers are capable of driving two standard TTL loads and 55pf.
R/W	43	I/O	This signal is generated by the CPU to control the direction of data transfers on the data bus. This line is high except when the CPU is writing to memory, an internal I/O register or an external device. When the AEC Or DMA/ signal is low, the R/W becomes tri-state.
RH0	44	IN	This clock is a TTL compatible input used for internal device operation and as a timing reference for communicating with the system data bus. Two internal clocks are generated by the device; phase two (PH2) is in phase with RH0 and phase one (PH1) is 180 degrees out of phase with RH0.
PC/	53	OUT	This output line is a strobe signal and is Centronics interface compatible. The signal goes low following a read or write access of PORT D.
PRD0-PRD7 PRB0-PRB7 PRA0-PRA7	45 thru 52 54 thru 61 62 thru 61	I/O I/O I/O	These are three 8-bit ports with each of their lines having a passive pull-up (min. 3K ohm) as well as active pull-up and pull-down transistors. Each individual port line may be programmed to be either input or output.
PRC2	70	I/O	This line corresponds to PORT C, bit 2. It has passive pull-up (min. 3k ohm) as well as active pull-up and pull- down transistors. The line can be configured as input or output. PRC2 becomes the external shift register clock when the UART is configured to operate in the synchronous mode, otherwise PRC2 operates as normal.
PRC3	71	OUT	This signal is an open drain output with a. passive pull-up (1K ohm min). It corresponds to bit 3 of PORT C. When this port bit is set as an input, the PRC3 line is driven low; reading the port bit will give a high. If configured as an output, reading this port bit will not give the status of the PRC3 line but the value previously written on the PORT C data reg. bit 3.
PRC46	72	I/O	This is an open drain bi-directional signal with a passive pull-up (1K ohm min). Bit 6 of PORT C is always configured as an input; the bit will give the status of the PRC46 line anytime the the port is read, regardless of what is written in the data direction register. If bit 4 of PORT C is set as an input, the PRC46 line will be pulled low; reading the port bit will give a high. If bit 4 is configured as an output, PRC46 will be pulled low if hit 4 in the port data register is high, otherwise the PRC46 line will float to a high.