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System Specification for C65Fred BowenMarch 1, 1991

RESTR/ 80 IN This input is tied to a 3K ohm (min.) passive pull-up. A bounce eliminator circuit is used on this pin to remove any bounce during its fal ling transition, if the pin is tied to a contact closure. If the device sees a negativetransition on this pin, it will immediately assert the NMI/ line to start a Non-Maskable Interrupt sequence. The device will ignore any subsequent transitions on the RESTR/ line until 4.2ms has elapsed, at which time the NMI/ line is deasserted.
EXTRST/ 81 OUT This output is an open drain ou (1K ohm pull-up, This pin will only go to a low state during power-up, and will stay low until .9 seconds after VDD has reached its operating voltage.
RESET/ 82 I/O The Reset line (RESET/) is an open drain bidirectional signal. A passive pull-up (1K ohm minimum) is tied on this pin, allowing any external source to initialize the device. A low on RESET/ will instantly initialize the internal 65CE02 and all internal registers. All port pins are set as inputs and port registers to zero (a read of the ports will return all highs because of passive pull-ups); all timer control registers are set to zero and all timer latches to ones. All other registers are reset to zero. During power-up RESET/ is held low and will go high .9 seconds after VDD reaches the operating voltage. If pulled low during operation, the c rrently executing opcode will be terminated. The B and Z registers will be cleared. The stack pointer will be set to "byte" mode, with the stack page set to page 1. The processor statu bits E and I will be set. When the high transition is detected the reset sequence begins on the CPU cycle. The first four cycles of the reset sequence do nothing. Then the program counter bytes PCL and PCH are loaded from memory addresses FFFC and FFFD, and normal program execution begins.


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Read the small print. Last updated August 10, 2001.