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System Specification for C65Fred BowenMarch 1, 1991

2.3.3.3 Register Description

This device contains a total of 41 I/O peripheral registers which can be accessed after the following conditions are met. In an access cycle, the device must be in a non-mapped mode (MAP/ line is not asserted), the IO/ line must be in an active low state and the A0-A3, A8 and A9 address-lines must contain the valid address of the register to be accessed. In addition, the state of the R/W line will indicate whether a read (R/W is "high") write (R/W is "low") cycle is under way.

A9 A8 ...A3 A2 A1 A0 HEX ADDRREG SYMBOLREGISTER NAME
0 0 0 0 0 0 0X0 PRA Peripheral Data Reg A
0 0 0 0 0 1 0X1 PRB Peripheral Data Reg B
0 0 0 0 1 0 0X2 DDRA Data Direction Reg A
0 0 0 0 1 1 0X3 DDRB Data Direction Reg B
0 0 0 1 0 0 0X4 TA LO Timer A Low Register
0 0 0 1 0 1 0X5 TA HI Timer A High Register
0 0 0 1 1 0 0X6 TB LO Timer B Low Register
0 0 0 1 1 1 0X7 TB HI Timer B High Register
0 0 1 0 0 0 0X8 TODATS TODA 10ths Sec Register
0 0 1 0 0 1 0X9 TODAS TODA Seconds Register
0 0 1 0 1 0 0XA TODAM TODA Minutes Register
0 0 1 0 1 1 0XB TODAH TODA Hours-AM/PM Reg
0 0 1 1 0 0 0XC SDRA SERIALA Data Register
0 0 1 1 0 1 0XD ICRA INTERRUPTA Control Reg.
0 0 1 1 1 0 0XE CRA Control Register A
0 0 1 1 1 1 0XF CRB Control Register B
 
0 1 0 0 0 0 1X0 PRC Peripheral Data Reg C
0 1 0 0 0 1 1X1 PRD Peripheral Data Reg D
0 1 0 0 1 0 1X2 DDRC Data Direction Reg C
0 1 0 0 1 1 1X3 DDRD Data Direction Reg D
0 1 0 1 0 0 1X4 TC LO Timer C Low Register
0 1 0 1 0 1 1X5 TC HI Timer C High Register
0 1 0 1 1 0 1X6 TD LO Timer D Low Register
0 1 0 1 1 1 1X7 TD HI Timer D High Register
0 1 1 0 0 0 1X8 TODBTS TODB 10ths of Sec Reg.
0 1 1 0 0 1 1X9 TODBS TODB Seconds Register
0 1 1 0 1 0 1XA TODBM TODB Minutes Register
0 1 1 0 1 1 1XB TODBH TODB Hours-AM/PM Reg.
0 1 1 1 0 0 1XC SDRB SERIALB Data Register
0 1 1 1 0 1 1XD ICRB INTERRUPTB Control Reg.
0 1 1 1 1 0 1XE CRC Control Register C
0 1 1 1 1 1 1XF CRD Control Register D
 
1 0 0 0 0 0 2X0 DREG Receive/Transmit Data Reg
1 0 0 0 0 1 2X1 URSR UART Status Register
1 0 0 0 1 0 2X2 URCR UART Control Register
1 0 0 0 1 1 2X3 BRLO Baud Rate Timer LO Reg.
1 0 0 1 0 0 2X4 BRHI Baud Rate Timer HI Reg.
1 0 0 1 0 1 2X5 URIEN UART IRQ/NMI Enable Reg.
1 0 0 1 1 0 2X6 URIFG UART IRQ/NMI Flag Reg.
1 0 0 1 1 1 2X7 PRE Peripheral Data Reg. E
1 0 1 0 0 0 2X8 DDRE Data Direction E
1 0 1 0 0 1 2X9 FSERIAL Fast Serial Bus Control

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