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System Specification for C65Fred BowenMarch 1, 1991

The functional description of the memory mapper follows in section 2.3.4.
The Fast Serial register is described in section 2.3.5

2.3.3.3.1 REGISTER BIT ALLOCATION

REGISTER BIT ALLOCATION
TABLE 2
R/W REG NAME D7 D6 D5 D4 D3 D2 D1 D0
R/W 0X0 PRA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
R/W 0X1 PRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
R/W 0X2 DDRA DPA7 DPA6 DPA5 DPA4 DPA3 DPA2 DPA1 DPA0
R/W 0X3 DDRB DPB7 DPB6 DPB5 DPB4 DPB3 DPB2 DPB1 DPB0
READ 0X4 TA LOTIMER TAL7 TAL6 TAL5 TAL4 TAL3 TAL2 TAL1 TAL0
READ 0X5 TA HI TAH7 TAH6 TAH5 TAH4 TAH3 TAH2 TAH1 TAH0
READ 0X6 TB LO TBL7 TBL6 TBL5 TBL4 TBL3 TBL2 TBL1 TBL0
READ 0X7 TB HI TBH7 TBH6 TBH5 TBH4 TBH3 TBH2 TBH1 TBH0
WRITE 0X4 TA LOPRESCALER PAL7 PAL6 PAL5 PAL4 PAL3 PAL2 PAL1 PAL0
WRITE 0X5 TA HI PAH7 PAH6 PAH5 PAH4 PAH3 PAH2 PAH1 PAH0
WRITE 0X6 TB LO PBL7 PBL6 PBL5 PBL4 PBL3 PBL2 PBL1 PBL0
WRITE 0X7 TB HI PBH7 PBH6 PBH5 PBH4 PBH3 PBH2 PBH1 PBH0
READ 0X8 TODATSTOD TIMER 0 0 0 0 TA8 TA4 TA2 TA1
READ 0X9 TODAS (*) 0 SAH4 SAH2 SAH1 SAL8 SAL4 SAL2 SAL1
READ 0XA TODAM (*) 0 MAH4 MAH2 MAH1 MAL4 MAL4 MAL2 MAL1
READ 0XB TODAH APM 0 0 HAH HAL8 HAL4 HAL2 HAL1
  (*) IN TEST MODE: WILL READ DIVIDER STAGE OUTPUTS
WRITE 0X8 TODATSTOD TIMER 0 0 0 0 TA8 TA4 TA2 TA1
WRITE 0X9 TODAS 0 SAH4 SAH2 SAH1 SAL8 SAL4 SAL2 SAL1
WRITE 0XA TODAM 0 MAH4 MAH2 MAH1 MAL4 MAL4 MAL2 MAL1
WRITE 0XB TODAH APM 0 0 HAH HAL8 HAL4 HAL2 HAL1
  IF CRB ALARM BIT=1, ALARM REGISTER IS WRITTEN
IF CRB ALARM BIT=0, TOD REGISTER IS WRITTEN



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