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System Specification for C65Fred BowenMarch 1, 1991

2.3.5 Peripheral Control Functions

2.3.5.1 I/O Ports

Ports A, B and D each consist of an 8-bit Peripheral Data Register (PR) and an 8-bit Data Direction Register (DDR). Port E consists of a 2-bit PR and DDR registers. If a bit in the DDR is set to one, the corresponding bit in the PR is an output, if a DDR bit is set to a zero, the corresponding PR bit is defined as an input. On a READ, the PR bit reflects the information present on the actual port pins (PRA0-PRA7,PRB0-PRB7,PRC2,PRD0-PRD7, PRE0-PRE1) for both input and output bits. All ports have passive pull-up devices as well as active pull-ups, providing both CMOS and TTL compatibility. in addition to normal I/O operation, PRB6,PRB7,PRD6 and PRD7 also provide timer output functions (refer to Control Register section, 2.5.8).

Only bit PC2 and DPC2 of PORT C meet the above description. The other bits function as described in the following.

PC0,PC1 These signals are simply a register bits. When read, they will reflect the value previously written to the PRC register.
PC4 This bit is a "high" if it's configured as input (DPC4 is a "low").

If configured as output (DPC4 is a "high"), the bit will reflect its previous written value when PORT C is read. Then the PRC46 pin is pulled "low" if PC4 is "high"; otherwise, PRC46 is pulled-up through passive resistor.

PC5 This bit is a "high" if it's configured as input (DPC5 is a "low").

If configured as output (DPC3 is a "high"), the bit reflect its previous written value when PORT C is read. Then the PRC57 pin is pulled "low" if PCs is "high"; otherwise, PRC57 is pulled-up through passive resistor.

PC6,PC7These bits are always configured as inputs. When PORT C (PRC) is read, PC6 and PC7 will reflect the values on the PRC46 and PRC57 pins, respectively.

2.3.5.2 Handshaking

Handshaking on data transfers can be accomplished using the PC/ output pin and either the FLAGA/ or FLAGB/ input pin. The PC/ line will go low and stay low for two cycles, two cycles after a read or write to PORT D. This is required to meet Centronics Parallel Interface specs. The PC/ line can be used to indicate "data ready" at PORT D or "data accepted" from PORT D. Handshaking on 16-bit data transfers (using either PORT A or B and then PORT D) is possible by always reading or writing PORT A or PORT B first. The FLAG/ lines are negative edge sensitive inputs which can be used for receiving the PC/ output from other 4510 devices, or as general purpose interrupt inputs. A negative transition on FLAGA/ or FLAGB/ will set the FLAGA or FLAGB interrupt bits, respectively.



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