|System Specification for C65||Fred Bowen||March 1, 1991|
Each interval timer consists of a 16-bit read-only Timer Counter and a 16-bit write-only Timer Latch (prescaler). Data written to the timer are latched in the Timer Latch, while data read from the timer are the present contents of the Timer Counter. The timers can be used independently or - linked in pairs for extended operations (TIMER A may be linked with Timer B; TIMER C may be linked with TIMER D). The various timer modes allow genera- tion of long time delays, variable width pulses, pulse trains and variable frequency waveforms. Utilizing the CNT inputs, the timers.can count ext6r- nal pulses or measure frequency, pulse witdth and delay times of external signals. Each timer has an associated control register, providing indepen- dent control of the following functions (see bits functional description in section 2.5.8 below):
Each timer may be started or stopped by the microprocessor at any time by writing to the START/STOP bit of the corresponding control register (CRA, CRB, CRB or CRC).
PRB, PRD On/Off
Control bits allow any of the timer outputs to appear on a PORT 3 or PORT D output line (PRB6 for TIMER A, PRB7 for TIMER B, PRD6 for TIMER C and PRD7~for TIMER D). Note that this funtion overrides the DDRB control bit and forces the appropriate PB or PC line to be an output.
Control bits select the outputs applied to PORT B and PORT D. On every timer underflow the ouput can either toggle or generate a single positive pulse of one cycle duration. The Toggle output is set high whenever the appropiate timer is started and is set low by RESET/.
Control bits select either time= mode. In one-shot mode, the timer will count down from the latched value to zero, generate an interrupt, reload the latched value, then ston. in continuous mode, the timer will count from the latched value to zero, generate an interrupt, reload the latched value and repeat the procedure continuously.
A strobe bit allows the timer latch to be loaded into the timer counter at any time, whether the timer is running or not.
Control bits allow selection of the clock used to decrement the timer. TIMER A or TIMER C can count CIMHZ clock pulses or external pulses applied to the CNTA or CNTB, respectively. The ClMHZ clock is obtained after internally dividing the C7MHZ by a factor of seven.
TIMER B can count ClMHZ clock pulsest external pulses applied to the CNTA input, TIMER A underflow pulses or TIMER A underflow pulses while the CNTA pin is held high.
|This page has been created by Sami Rautiainen.|
|Read the small print.||Last updated August 10, 2001.|