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System Specification for C65Fred BowenMarch 1, 1991

TIMER D can count CIMHZ clock pulses, external pulses applied to the CNTB input, TIMER C underflow pulses or TIMER C underflow pulses while the CNTB pin is held high.

The timer latch is loaded into the timer on any timer underflow, on a force load or following a write to the high byte of the prescaler while the timer is stopped. If the timer is running, a write to the high byte will load the timer latch, but not reload the counter.

2.3.5.4 Time of Day Clocks (TODA, TODB)

The TODA and TODB clocks are special purpose timers for real-time applications. Each clock, TODA or TODB, consists of a 24-hour (AM/PM) clock with 1/10th second resolution. Each is organized into four registers: 10ths of seconds (TODATS, TODBTS), Seconds (TODAS, TODBS), Minutes (TODAM, TODBM) and Hours (TODAH, TODBH). The AM/PM flag is in the MSB of the Hours register for easy testing. Each register reads out in BCD format to simpl fy conversion for driving displays, etc. Each TOD requires a 10HZ clock input to keep accurate timing. This 10HZ clock is generated by dividing the C7MHz clock input by a factor'of 102273 for NTSC (60Hz) applications, or a factor of 101339 for PAL (50Hz) applications. The divider ratio is selected by the TODA IN and the TODB IN bits of the Control Registers, CRA and CRC, respectively (see 2.5.8).

In addition to time-keeping, a programmable ALARM is provided for generating an interrupt at the de-sired time, from either of the TOD clocks. The ALARM registers registers are located at the same addresses as the corresponding TODA and TODB registers. Access to the ALARM is governed by bit 7 in the Control Registers CRB and CRD. The ALARM registers are write-only any read of a TOD address will read time regardless of the state of the ALARM access control bits.

A specific sequence of events musl be followed for proper setting and reading of each TOD. A TOD is automatically stopped whenever a write to the corresponding Hours register occurs. The TOD will not start again until after a write to the proper 10ths of seconds register. This assures that a TOD will always start at the desired time. Since a carry from one stage to the next can occur at any time with respect to a read operation, a latching function is included to keen all Time of Day information constant during a read sequence. All four registers of each TOD latch on a read of the corresponding Hours register and remain latched until after a read of the corresponding 10ths of second register. A TOD continues to count when the output registers are latched. If only one register is to be read, there is no carry problem and the register can be read "on the fly", provided that any read of the Hours register if followed by a read of the proper 10ths of seconds, to disable the latching.

2.3.5.5 Serial Ports (SDRA, SDRB)

Each serial port is a buffered, 8-bit synchronous shift register system. A control bit (CRA SPA bit, CRC SPB bit) select$ input or output mode for either the SDRA or SDRB port.

In input mode, data on the SPA or SPB pin is shifted into the corresponding shift register on the rising edge of the signal applied to the CNTA or CNTB pin, respectively. After 8 CNTA pulses , the data in the shift register is dumped into the SERIALA Data Register (SDRA) and an interrupt is



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