[Prev] [Next] [Contents] [Commodore] [New] [Search] [Home]

System Specification for C65Fred BowenMarch 1, 1991

2.3.7.3 65CE02 Interrupts

There are four basic interrupt sources on the CSG 4502. These are RES*, IRQ*, NMI*, and So, for Reset, Interrupt Request, Non-Maskable Interrupt, and Set Overflow. The Reset is a hard non-recoverable interrupt that stops everything. The IRQ is a "maskable" interrupt, in that its occurance can be prevented. The NMI is "non-maskable", and if such an event occurs, cannot be prevented. The SO, or Set Overflow, is not really an interrupt, but causes an externally generated condition, which can be used for control of program flow.

One important design feature, which must be remembered is that no interrupt can occur immediately after a one-cycle opcode. This is very important, because there are times when you want to temporarily prevent interrupts from occurring. The best example of this is, when setting a 16-bit stack pointer, you do not want an interrupt to occur between the times you set the low-order byte, and the high-order byte. If it could happen, the interrupt would do stack writes using a pointer that was only partially set, thus, writing to an unwanted area.

IRQ*

The IRQ* (Interrupt ReQuest) input will cause an interrupt if it is at a low logic level, and the I processor status flag is reset. The interrupt sequence will begin with the first SYNC after a multiple-cycle opcode. The two program counter bytes PCH and PCL, and the processor status register P, are pushed onto the stack. (This causes the stack pointer SP to be decremented by 3.) Then the program counter bytes PCL and PCH are loaded from memory addresses FFFE and FFFF, respectively.

An interrupt caused by the IRQ* input, is similar to the BRK opcode, but differs, as follows. The program counter value stored on the stack points to the opcode that would have been executed, had the interrupt not occurred. On return from interrupt, the processor will return to that opcode. Also, when the P register is pushed onto the stack, the B or "break" flag pushed, is zero, to indicate that the interrupt was not software generated.

NMI*

The NMI* (Non-Maskable Interrupt) input will cause an interrupt after receiving, a high to low transition The interrupt sequence will begin with the first SYNC after a multiple-cycle opcode. NMI* inputs cannot be masked by the processor status register I flag. The two program counter bytes PCH and PCL, and the processor status register P, are pushed onto-the stack. (This causes the stack pointer SP to be decremented by 3.) Then the program counter bytes PCL and PCH are loaded from memory addresses FFFA and FFFB.

As with IRQ*, when the P register is pushed onto the stack, the B or "break" flag pushed, is zero, to indicate that the interrupt was not software generated. A

RES*

The RES* (reset) input will cause a hard reset instantly as it is brought to a low logic level. This effects the following conditions. The currently executing opcode will be terminated. The B and Z registers will be cleared. The stack pointer will be set to "byte" mode, with the stack page set to page 1. The processor status bits E and I will be set.

The RES* input should be held low for at least 2 clock cycles. But once brought high, the reset sequence begins on the CPU cycle. The first four cycles of the.reset sequence do nothing. Then the program Counter bytes PCL and PCH are loaded from memory addresses FFFC and FFFD, and normal program execution begins.

SO

The SO (set overflow) input does, as its name implies, set the overflow or V processor status flag. The effect is immediate as this active low signal is brought or held at a low logic level. Care should be taken if this signal is used, as some of the opcodes can set or reset the overflow flag, as well. NOTE: The SO pin has been removed for C65.



[Prev] [Next] [Contents] [Commodore] [New] [Search] [Home]
This page has been created by Sami Rautiainen.
Read the small print. Last updated April 06, 2006.