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8520A BLOCK DIAGRAM AND REGISTER MAP


BLOCK DIAGRAM

RS3RS2RS1RS0REG   NAME  DESCRIPTION
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
  PRA
  PRB
  DDRA
  DDRB
  TA LO
  TA HI
  TB LO
  TB HI
  



  SDR
  ICR
  CRA
  CRB
  Peripheral Data Register A
  Peripheral Data Register B
  Data Direction Register A
  Data Direction Register B
  Timer A Low Register
  Timer A High Register
  Timer B Low Register
  Timer B High Register
  Event LSB
  Event 8-15
  Event MSB
  No Connect
  Serial Data Register
  Interrupt Control Register
  Control Register A
  Control Register B


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This page has been created by Frank Kontros.
Last updated May 14th, 1999.